Overseeing the physical design of deep submicron digital ASICs; * ASIC design tools, including ... Leading an engineering team. Can work remotely Supervises Preferred Skills: N/A #LI-AM4 Benefits ...
Overseeing the physical design of deep submicron digital ASICs; * ASIC design tools, including ... Leading an engineering team. Can work remotely Supervises Preferred Skills: N/A #LI-AM4 Benefits ...
SMTS Analog Design Engineer
Santa Clara, CA · On-site +1
$238K/yr
Drive/develop ASIC design flows and scripts. Analyze complex digital design problems and propose ... mental or physical disability, national origin, race, religion, political and/or third-party ...
SMTS Analog Design Engineer
Santa Clara, CA · On-site +1
$238K/yr
Drive/develop ASIC design flows and scripts. Analyze complex digital design problems and propose ... mental or physical disability, national origin, race, religion, political and/or third-party ...
Sr. ASIC EDA Workflow Engineer
Sunnyvale, CA · On-site +1
Hands-on ASIC engineering experience, that includes knowledge of VLSI/SoC chip design and ... verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence. * Knowledge of ...
Sr. ASIC EDA Workflow Engineer
Sunnyvale, CA · On-site +1
Hands-on ASIC engineering experience, that includes knowledge of VLSI/SoC chip design and ... verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence. * Knowledge of ...
Principal mmWave Design Engineer (Power Amplifiers) - TeraWave
San Diego, CA · On-site +1
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Develop Analog model for verification methodologies for ASIC verification and requirements ...
Principal mmWave Design Engineer (Power Amplifiers) - TeraWave
San Diego, CA · On-site +1
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Develop Analog model for verification methodologies for ASIC verification and requirements ...
Principal mmWave Design Engineer (Power Amplifiers) - TeraWave
Bodega Bay, CA · On-site +1
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Develop Analog model for verification methodologies for ASIC verification and requirements ...
Principal mmWave Design Engineer (Power Amplifiers) - TeraWave
Bodega Bay, CA · On-site +1
$230K - $322K/yr
A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Develop Analog model for verification methodologies for ASIC verification and requirements ...
Bluespec Design Engineer (Haskell)
Mountain View, CA · On-site +1
$175K - $362K/yr
Prior hardware design experience - ASIC or FPGA. If you already understand clock domains ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...
Bluespec Design Engineer (Haskell)
Mountain View, CA · On-site +1
$175K - $362K/yr
Prior hardware design experience - ASIC or FPGA. If you already understand clock domains ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...
ASIC Engineer, Power Management Design Verification
Sunnyvale, CA · On-site +1
$178K/yr
ASIC Engineer, Power Management Design Verification Responsibilities: * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
ASIC Engineer, Power Management Design Verification
Sunnyvale, CA · On-site +1
$178K/yr
ASIC Engineer, Power Management Design Verification Responsibilities: * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
High-Speed Analog Layout Design Engineer
San Jose, CA · On-site +1
$239K/yr
Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and ... Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs ...
Quick apply
High-Speed Analog Layout Design Engineer
San Jose, CA · On-site +1
$239K/yr
Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and ... Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs ...
High-Speed Analog Layout Design Engineer
Irvine, CA · On-site +1
$217K/yr
Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and ... Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs ...
Quick apply
High-Speed Analog Layout Design Engineer
Irvine, CA · On-site +1
$217K/yr
Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and ... Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs ...
Senior SoC Power Analysis & Optimization Engineer
Mountain View, CA · On-site +1
$175K - $450K/yr
Work with physical design teams to evaluate implementation-related power trade-offs. * Define ... Experience with ASIC low-power design techniques. * Experience performing RTL and gate-level power ...
Senior SoC Power Analysis & Optimization Engineer
Mountain View, CA · On-site +1
$175K - $450K/yr
Work with physical design teams to evaluate implementation-related power trade-offs. * Define ... Experience with ASIC low-power design techniques. * Experience performing RTL and gate-level power ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site +1
$230K - $322K/yr
Collaborate with RFIC, mmWave, ASIC, Package Layout, and SoC architecture teams on package ... physical Benefits * Benefits include: Medical, dental, vision, basic and supplemental life ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site +1
$230K - $322K/yr
Collaborate with RFIC, mmWave, ASIC, Package Layout, and SoC architecture teams on package ... physical Benefits * Benefits include: Medical, dental, vision, basic and supplemental life ...
Senior IC Package Design Engineer - TeraWave
Bodega Bay, CA · On-site +1
$230K - $322K/yr
Collaborate with RFIC, mmWave, ASIC, Package Layout, and SoC architecture teams on package ... physical Benefits * Benefits include: Medical, dental, vision, basic and supplemental life ...
Senior IC Package Design Engineer - TeraWave
Bodega Bay, CA · On-site +1
$230K - $322K/yr
Collaborate with RFIC, mmWave, ASIC, Package Layout, and SoC architecture teams on package ... physical Benefits * Benefits include: Medical, dental, vision, basic and supplemental life ...
Design Engineer
San Francisco, CA · On-site +1
$220K - $350K/yr
Without design engineers as influential voices in the company, none of this would be possible. And ... We fly remote teammates to SF for three to four days a month. Visa sponsorship. We sponsor visas:
Design Engineer
San Francisco, CA · On-site +1
$220K - $350K/yr
Without design engineers as influential voices in the company, none of this would be possible. And ... We fly remote teammates to SF for three to four days a month. Visa sponsorship. We sponsor visas:
Hot Cell Design Engineer
Santa Clara, CA · On-site +1
Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...
Hot Cell Design Engineer
Santa Clara, CA · On-site +1
Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...
Hot Cell Design Engineer
Santa Clara, CA · On-site +1
Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...
Hot Cell Design Engineer
Santa Clara, CA · On-site +1
Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...
Lead Substation Physical Engineer - REMOTE
Los Angeles, CA · Remote
$110K - $145K/yr
Remote US Ready to make a difference ... ICF is seeking an experienced Substation Physical Engineer to lead the design and execution of high ...
Lead Substation Physical Engineer - REMOTE
Los Angeles, CA · Remote
$110K - $145K/yr
Remote US Ready to make a difference ... ICF is seeking an experienced Substation Physical Engineer to lead the design and execution of high ...
Project Design Engineer (SCADA)
Berkeley, CA · On-site +1
$85K - $105K/yr
Generous time off and holiday policy Remote flexibility Flexible time off Comprehensive benefits ... genetic information, physical or mental disability, military/ veteran status, or any other ...
Project Design Engineer (SCADA)
Berkeley, CA · On-site +1
$85K - $105K/yr
Generous time off and holiday policy Remote flexibility Flexible time off Comprehensive benefits ... genetic information, physical or mental disability, military/ veteran status, or any other ...
Design Engineer V
Sunnyvale, CA · On-site +1
US - Remote Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on Meta's AR Product Team, you will be responsible for driving world-class ...
Design Engineer V
Sunnyvale, CA · On-site +1
US - Remote Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on Meta's AR Product Team, you will be responsible for driving world-class ...
Project Design Engineer (SCADA)
Berkeley, CA · On-site +1
$85K - $105K/yr
... • Remote flexibility • Flexible time off • Comprehensive benefits package • Career ... genetic information, physical or mental disability, military/ veteran status, or any other ...
Project Design Engineer (SCADA)
Berkeley, CA · On-site +1
$85K - $105K/yr
... • Remote flexibility • Flexible time off • Comprehensive benefits package • Career ... genetic information, physical or mental disability, military/ veteran status, or any other ...
Senior/Principal Physical Verification Engineer
Irvine, CA · On-site +1
$150K - $250K/yr
Senior to Principal Full-Chip Physical Verification Engineer roles Locations ... San Jose, CA (preferred) or Irvine, CA (HQ) or remote Key Responsibilities Team & Project ...
Quick apply
Senior/Principal Physical Verification Engineer
Irvine, CA · On-site +1
$150K - $250K/yr
Senior to Principal Full-Chip Physical Verification Engineer roles Locations ... San Jose, CA (preferred) or Irvine, CA (HQ) or remote Key Responsibilities Team & Project ...
Remote Asic Physical Design Engineer information
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Full-time
Posted 4 days ago
Advanced Micro Devices rating
8.6
Based on 13 frontline employees who took The Breakroom Quiz
27th of 159 rated electronics manufacturers
Job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
Job Role and Responsibility: AMD, Inc., is hiring Sr. Manager Silicon Design Engineering to Develop and establish timing closure methodologies and strategies for SoC and IP blocks to ensure compliance with requirements and provide technical guidance to execution teams. Oversee STA closure for complex SoC designs featuring chiplet and 3D stack interfaces. Leverage extensive knowledge and experience in physical design and full-chip timing to tackle large, cutting-edge designs, ensuring high-quality, on time delivery. Understand the SoC as an integrated system while optimizing for performance and power. Collaborate cross-functionally with IP, Domain, CAD, and Methodology teams to identify and address intricate technical challenges and risks, and create solutions to meet product specifications. Share knowledge and contribute to various SoC functions. As the overall STA and clocking lead, take responsibility for architectural analysis and the scoping/assessment of feature changes. Partner closely with design teams to refine clocking, area and floorplan, set timing targets, and secure performance sign-offs. Assist Post-Silicon teams with debugging and resolving timing issues. Utilize knowledge of computers and electronics, including circuit boards, processors, chips, and electronic equipment, as well as knowledge of design techniques, tools, and principles. Apply knowledge of engineering principles, best practices, and technologies to the design, development, and testing of various company proprietary products.
Can work remotely.
Supervises.
Multiple openings. Qualified applicants click “APPLY NOW” button to apply online.
Travel required: NO
Qualifications: Degree required
Master’s degree or foreign equivalent in Electronics Engineering, Computer Science, Computer Engineering, or Electrical Engineering or related field.
Qualifications: Amount and type of experience required: Four (4) years of experience in the job offered or a closely related engineering role.
Alternate combination of education and experience: Employer will alternatively accept a Bachelor’s degree or foreign equivalent in Electronics Engineering, Computer Science, Computer Engineering, or Electrical Engineering or related field and six (6) years of experience in the job offered or a closely related engineering role.
Specific skills required: The following skills are required:
Position requires four (4) years of experience in the following:
- Using Computer-Aided Design (CAD) tools to oversee the entire chip design process;
- Overseeing the physical design of deep submicron digital ASICs;
- ASIC design tools, including synthesis, simulation, equivalence checking, and static timing analysis;
- Using back-end Electronic Design Automation (EDA) tools to oversee the physical implementation of a chip design;
- Scripting in TCL, Perl or Python to automate repetitive steps in the design process, such as logic synthesis, timing analysis, or place-and-route;
- Overseeing Static Timing Analysis (STA) closure to ensure a chip design will function correctly at its target speed;
- Owning global clock tree construction and analysis for best PPA;
- Using Physical Design Closure, including floor planning, placement, clock tree synthesis (CTS), routing, and timing closure;
- Managing silicon design projects; and
- Leading an engineering team.
Can work remotely
Supervises
Preferred Skills: N/A
#LI-AM4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMEWhat Advanced Micro Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US