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Physical Design Intern Jobs in California (NOW HIRING)

Tenstorrent University Jobs

$50/hr

As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating with top engineers to optimize some of the most advanced silicon in the world. This role is onsite ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist ...

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Physical Design Intern information

See California salary details

$9

$19

$36

How much do physical design intern jobs pay per hour?

As of Aug 12, 2026, the average hourly pay for physical design intern in California is $19.12, according to ZipRecruiter salary data. Most workers in this role earn between $14.23 and $21.35 per hour, depending on experience, location, and employer.

What kinds of projects or tasks can I expect as a physical design intern?

As a Physical Design Intern, you can expect to assist with tasks such as floorplanning, placement and routing, timing analysis, and design rule checking as part of the ASIC or SOC development flow. You'll typically work closely with experienced physical design engineers, learning industry-standard tools and participating in meetings where design challenges and optimization strategies are discussed. Interns may also be given opportunities to automate tasks through scripting or contribute to documentation for internal processes. This role provides a hands-on introduction to the semiconductor industry and allows you to gain practical skills that are highly valuable for entry-level positions or future specialization within chip design.

What are the key skills and qualifications needed to thrive as a physical design intern?

To thrive as a Physical Design Intern, you should have a solid understanding of digital integrated circuit fundamentals, basic knowledge of VLSI concepts, and be working toward a degree in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly advantageous. Strong analytical thinking, attention to detail, and effective communication skills will set you apart when collaborating with team members and troubleshooting complex design issues. These skills are crucial for ensuring high-quality chip designs that meet performance, area, and power requirements in real-world hardware development.

What is a physical design intern?

A Physical Design Intern assists in the back-end design and implementation of integrated circuits (ICs). Responsibilities typically include floorplanning, placement, routing, timing analysis, and power optimization. Interns work with tools like Cadence or Synopsys and collaborate with design and verification teams to meet performance, power, and area goals. This role provides hands-on experience with the ASIC or FPGA design flow, helping interns develop industry-relevant skills.

What are the most commonly searched types of Physical Design jobs in California? The most popular types of Physical Design jobs in California are:
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What cities in California are hiring for Physical Design Intern jobs? Cities in California with the most Physical Design Intern job openings:
Physical Design Intern jobs near you
Infographic showing various Physical Design Intern job openings in California as of August 2026, with employment types broken down into 1% As Needed, 77% Full Time, 17% Part Time, 2% Temporary, 2% Contract, and 1% Nights. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution, with an average salary of $39,777 per year, or $19.1 per hour.

Physical Design Intern

SK hynix memory solutions America Inc.

San Jose, CA • On-site

$35 - $45/hr

Other

This job post has expired today. Applications are no longer accepted.

Job description

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role: Join our Physical Design team to help deliver next-generation SSD controller chips. As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL designs into functional physical layouts. You will gain hands-on experience in the complete ASIC flow from synthesis to tape-out, working on real projects in a fast-paced, innovative environment.

Responsibilities:

  • Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
  • Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
  • Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
  • Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
  • Developing entire P&R/physical verification/IR-EM flows.
  • Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
  • Help generate and maintain physical design scripts, utilities, and documentation for the team.

Minimum Qualifications:

  • Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
  • Familiarity with the basic stages of the ASIC physical design flow.
  • Academic or project experience with scripting languages such as Python, Perl, or TCL.
  • Strong analytical and problem-solving skills with a high attention to detail.

Preferred Qualifications:

  • Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
  • Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
  • Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
  • Knowledge of low-power design techniques and power intent formats (UPF/CPF).
  • Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.


COMPENSATION: $35/hr - $45/hr

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