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Physical Design Engineer Intern Jobs in California

Search Tactics LLC

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the ...

search-tactics

Physical Design Engineer

San Jose, CA · On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is okay C2C Position Overview We are seeking an experienced Physical Design Engineer to support the ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Stellent IT LLC

Physical Design Engineer.

San Diego, CA · On-site

$144K - $148K/yr

Hello, Tittle-Physical Design Engineer Location- San Diego, California, San Jose, CA and Irvine, CA Job Type- Fulltime Physical Design Engineer We are looking for humble geniuses, who believe that ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

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Physical Design Engineer Intern information

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is a physical design engineer intern?

A physical design engineer intern is a student or entry-level professional gaining hands-on experience in the physical implementation of integrated circuits, including tasks like floorplanning, placement, routing, and timing analysis. They typically work with electronic design automation (EDA) tools and collaborate with engineering teams to optimize chip performance and manufacturability.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in California? The most popular types of Physical Design Engineer jobs in California are:
What are popular job titles related to Physical Design Engineer Intern jobs in California? For Physical Design Engineer Intern jobs in California, the most frequently searched job titles are:
What job categories do people searching Physical Design Engineer Intern jobs in California look for? The top searched job categories for Physical Design Engineer Intern jobs in California are:
What cities in California are hiring for Physical Design Engineer Intern jobs? Cities in California with the most Physical Design Engineer Intern job openings:
Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in California as of August 2026, with employment types broken down into 1% As Needed, 77% Full Time, 17% Part Time, 2% Temporary, 2% Contract, and 1% Nights. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution.

SSG Design Engineering Intern (Fall 2026)

Cadence Design Systems, Inc.

San Jose, CA • On-site

$35/hr

Full-time

Posted 25 days ago

Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 242 rated software companies

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern
The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.


The Cadence SSG Team is hiring graduates to join our R&D teams in San Jose, CA. This is an amazing opportunity to work as a Design Engineering Intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great SSG Team where you can make an impact that is visible.
This Design Engineering Intern position involves working on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product.


(a) Digital Design projects involve working on aspects of the logic design of the Janus NoC. It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.


(b) Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.

The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.


Position Requirements:
Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
Deep understanding of Digital Design and/or Design Verification Fundamentals
Excellent automation skills using Tcl, Perl, shell scripting
Excellent oral and written communications skills
Exposure to design automation tools is a plus

Internship will be based in San Jose location. Ideal candidates should be from local school near office.

The annual salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

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