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Physical Design Engineer Intern Jobs in California

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Physical Design Engineer

San Jose, CA · On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is okay C2C Position Overview We are seeking an experienced Physical Design Engineer to support the ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Apple

Physical Design Engineer

Bodega Bay, CA

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Altera

Physical Design Engineer

San Jose, CA

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

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Physical Design Engineer Intern information

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in California?

The most popular types of Physical Design Engineer jobs in California are:

What are popular job titles related to Physical Design Engineer Intern jobs in California?

For Physical Design Engineer Intern jobs in California, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Intern jobs in California look for?

The top searched job categories for Physical Design Engineer Intern jobs in California are:

What cities in California are hiring for Physical Design Engineer Intern jobs?

Cities in California with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in California as of August 2026, with employment types broken down into 1% As Needed, 73% Full Time, 20% Part Time, 5% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution.

Physical Design Engineer

search-tactics

San Jose, CA • On-site

$70 - $80/hr

Contractor

Re-posted 3 days ago

Job description

Position: Physical Design Engineer
Location: San Jose, CA Hybrid

Duration: 12 Months

VISA: H-1, GC, USC is okay C2C

Position Overview

We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams.

Key Responsibilities

Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

Optimize designs for power, performance, and area (PPA) throughout the synthesis and physical design flow.

Develop and improve floorplans using Cadence Innovus, ensuring efficient utilization and routing.

Collaborate with RTL, architecture, and design teams to provide feedback on timing, constraints, and implementation strategies.

Partner with physical implementation and place-and-route teams to achieve timing closure and design quality goals.

Analyze timing challenges, identify critical paths, and recommend design improvements to improve convergence.

Support physical implementation activities from synthesis through implementation while maintaining design quality and schedule objectives.

Required Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.

5+ years of experience in ASIC or SoC Physical Design.

Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.

Experience working on large, high-performance semiconductor designs with demanding timing requirements.

Strong knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.

Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.

Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.

Preferred Qualifications

Experience supporting complex SoC, AI, HPC, or accelerator designs.

Strong understanding of timing closure methodologies and synthesis-to-implementation correlation.

Familiarity with advanced implementation flows, design constraints, and physical optimization techniques.

Proven ability to collaborate with globally distributed engineering teams to deliver successful silicon implementations.