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Physical Design Engineer Intern Jobs in Riverside, CA

System Canada Technologies

Physical Design Engineer

Irvine, CA · On-site

$146K - $150K/yr

Physical design implementation at block or top level, low power techniques and timing closure Job Duties Include: - Will own all parts of the physical design process from netlist handoff to tapeout ...

Marvell

Principal, IC Digital Design Engineer

Irvine, CA · On-site

$146K/yr

You'll work closely with experts in architecture, verification, physical design, and systems to ... Engineering, Computer Engineering, or related field ; PhD is a plus. Preferred / Plus Skills

Phizenix

Digital Design Engineer

Irvine, CA · On-site

$180K - $250K/yr

: Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring ... and physical-design teams. Required Qualifications Education & Experience * B.S. or M.S. in ...

Marvell

Senior Staff Digital Design Engineer

Irvine, CA · On-site

Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the ... You'll work closely with experts in architecture, verification, physical design, and systems to ...

L3 Harris

Electrical Engineer Intern

Anaheim, CA

$71K - $132K/yr

Electrical Engineer Intern Job Code: 39061 Job Location: Anaheim, CA ... Participate in the design, development, and testing of high-voltage and high-power maritime power ...

Fluxergy

Firmware Engineer Intern

Irvine, CA · On-site

$20/hr

The intern will work closely with engineering teams to support firmware development activities ... design - lots of visibility! - Many of our current leaders started their career with Fluxergy!

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in Riverside, CA

Physical Design Engineer Intern information

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How much do physical design engineer intern jobs pay per hour?

As of Aug 24, 2026, the average hourly pay for physical design engineer intern in Riverside, CA is $20.15, according to ZipRecruiter salary data. Most workers in this role earn between $16.78 and $21.83 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in Riverside, CA?

The most popular types of Physical Design Engineer jobs in Riverside, CA are:

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For Physical Design Engineer Intern jobs in Riverside, CA, the most frequently searched job titles are:

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The top searched job categories for Physical Design Engineer Intern jobs in Riverside, CA are:

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Cities near Riverside, CA with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Riverside, CA as of August 2026, with employment types broken down into 29% Internship, 43% Full Time, 14% Part Time, and 14% Contract. Highlights an 100% In-person job distribution, with an average salary of $41,913 per year, or $20.2 per hour.

Principal Physical Design Engineer

Celero Communications, Inc.

Irvine, CA

$150K - $250K/yr

Full-time

Posted 7 days ago

Job description

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world's most advanced AI and data center infrastructure.

We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

Locations: San Jose, CA (preferred) or Irvine, CA (HQ)

Core Responsibilities
RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness. 

Key Qualifications
Must have 5+ years of relevant ASIC physical design experience (depending on degree level).
Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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