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Physical Design Engineer Intern Jobs in Riverside, CA

Marvell

Staff Physical Design Engineer

Irvine, CA · On-site

$146K - $150K/yr

... physical design methodologies, flows, and automation to improve productivity and design quality What We're Looking For * Bachelor's degree in Computer Science, Electrical Engineering or related ...

Integr8staff

Manufacturing Engineer Intern

Brea, CA

$23/hr

Job Title - Manufacturing Engineer Intern MUST HAVE Aerospace/ Defense Exp. Company Location -Near ... Design tooling, fixtures and jigs to improve manufacturing. Extend courteous support to always ...

Fluxergy

Firmware Engineer Intern

Irvine, CA · On-site

$20/hr

The intern will work closely with engineering teams to support firmware development activities ... design - lots of visibility! - Many of our current leaders started their career with Fluxergy!

Marvell

Senior Staff Digital Design Engineer

Irvine, CA · On-site

Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the ... You'll work closely with experts in architecture, verification, physical design, and systems to ...

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in Riverside, CA

Physical Design Engineer Intern information

See Riverside, CA salary details

$11

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$30

How much do physical design engineer intern jobs pay per hour?

As of Jul 13, 2026, the average hourly pay for physical design engineer intern in Riverside, CA is $20.15, according to ZipRecruiter salary data. Most workers in this role earn between $16.78 and $21.83 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a Physical Design Engineer Intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What does a Physical Design Engineer Intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in Riverside, CA? The most popular types of Physical Design Engineer jobs in Riverside, CA are:
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What cities near Riverside, CA are hiring for Physical Design Engineer Intern jobs? Cities near Riverside, CA with the most Physical Design Engineer Intern job openings:
Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Riverside, CA as of July 2026, with employment types broken down into 29% Internship, 43% Full Time, 14% Part Time, and 14% Contract. Highlights an 100% In-person job distribution, with an average salary of $41,913 per year, or $20.2 per hour.
Physical Design Engineer

Physical Design Engineer

System Canada Technologies

Irvine, CA

$146K - $150K/yr

Contractor

Re-posted 14 days ago

Job description

Company Description

SCT resources have a broad range of skills in different technologies. The large skill-set has been made possible by a conscious focus on strengthening our skills base. Every person selected for our team brings something new, something that adds to our offerings. We learn continuously, both on the job and through formal training programs.

Job Description

Job Description:

Physical design implementation at block or top level, low power techniques and timing closure

Job Duties Include:

- Will own all parts of the physical design process from netlist handoff to tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification

- Verify effects of crosstalk, IR drop and electromigration

- Very comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation

- Work very closely with logic designers, who are members of this same group, to build complex SOC's

Job Requirements:

- BSEE with 6+ (or MSEE with 3+) years related experience;

- Physical design knowledge, from netlist handoff to GDS tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification

- Experience with 45nm or 28nm technology

- Experience with low power techniques

- Experience with TCL and Perl

- Excellent communication and presentation skills

- Well organized, methodical and detail oriented

System Canada logo

About System Canada

Sourced by ZipRecruiter

System Canada delivers high end solutions in corporate world. Our resources have a broad range of skills in different technologies.The large skill-set has been made possible by a conscious focus on strengthening our skills base. Every person selected for our team brings something new, something that adds to our offerings. We learn continuously, both on the job and through formal training programs.

Industry

It services

Company size

11 - 50 Employees

Headquarters location

Toronto, ON, CA

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