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Physical Design Engineer Intern Jobs in Riverside, CA

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

$110K - $140K/yr

Work with physical design teams on floor planning, timing closure, and DFT implementation * Perform ... Collaborate with algorithm and application engineers on image tuning, optimization, and ...

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

$110K - $140K/yr

Work with physical design teams on floor planning, timing closure, and DFT implementation * Perform ... Collaborate with algorithm and application engineers on image tuning, optimization, and ...

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

Work with physical design teams on floor planning, timing closure, and DFT implementation * Perform ... Collaborate with algorithm and application engineers on image tuning, optimization, and ...

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

$110K - $140K/yr

Work with physical design teams on floor planning, timing closure, and DFT implementation * Perform ... Collaborate with algorithm and application engineers on image tuning, optimization, and ...

Fluxergy

Firmware Engineer Intern

Irvine, CA

$20/hr

The intern will work closely with engineering teams to support firmware development activities ... design - lots of visibility! - Many of our current leaders started their career with Fluxergy!

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

$110K - $140K/yr

Work with physical design teams on floor planning, timing closure, and DFT implementation * Perform ... Collaborate with algorithm and application engineers on image tuning, optimization, and ...

AEVEX

Design Engineer 3

Murrieta, CA · On-site

$133.90 - $147.90/hr

The Design Engineer 3 at AEVEX Aerospace is engaged in the design of aircraft structural and system ... The physical demands described here are representative of those that must be met by an employee to ...

AEVEX

Design Engineer 3

Murrieta, CA · On-site

$133.90 - $147.90/hr

The Design Engineer 3 at AEVEX Aerospace is engaged in the design of aircraft structural and system ... The physical demands described here are representative of those that must be met by an employee to ...

Fluxergy

Firmware Engineer Intern

Irvine, CA · On-site

$20/hr

The intern will work closely with engineering teams to support firmware development activities ... design - lots of visibility! - Many of our current leaders started their career with Fluxergy!

L3 Harris

Electrical Engineer Intern

Anaheim, CA · On-site

$71K - $132K/yr

Electrical Engineer Intern Job Code: 39061 Job Location: Anaheim, CA ... Participate in the design, development, and testing of high-voltage and high-power maritime power ...

Hirebridge

Entry-Level Structural Engineer | Intern

Orange, CA · On-site

$18 - $23.25/hr

You may be especially interested in seismic analysis for our West Coast offices or steel design for ... As a Structural Engineering Intern, you will work alongside experienced engineers on active ...

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in Riverside, CA

Physical Design Engineer Intern information

See Riverside, CA salary details

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How much do physical design engineer intern jobs pay per hour?

As of Sep 15, 2026, the average hourly pay for physical design engineer intern in Riverside, CA is $20.15, according to ZipRecruiter salary data. Most workers in this role earn between $16.78 and $21.83 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in Riverside, CA?

The most popular types of Physical Design Engineer jobs in Riverside, CA are:

What are popular job titles related to Physical Design Engineer Intern jobs in Riverside, CA?

For Physical Design Engineer Intern jobs in Riverside, CA, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Intern jobs in Riverside, CA look for?

The top searched job categories for Physical Design Engineer Intern jobs in Riverside, CA are:

What cities near Riverside, CA are hiring for Physical Design Engineer Intern jobs?

Cities near Riverside, CA with the most Physical Design Engineer Intern job openings:

Infographic showing various Physical Design Engineer Intern job openings in Riverside, CA as of September 2026, with employment types broken down into 29% Internship, 43% Full Time, 14% Part Time, and 14% Contract. Highlights an 100% In-person job distribution, with an average salary of $41,913 per year, or $20.2 per hour.

Digital Design Engineer

Irvine, CA • On-site

OmniVision Technologies
Software Development • 1 - 5K employees
Learn more about OmniVision Technologiesexternal

$110K - $140K/yr

Full-time

Re-posted 12 days ago

Job description

Key Responsibilities:
  • Design and implement sensor timing control logic and contribute to ISP system-level integration
  • Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs
  • Integrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture
  • Collaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation
  • Work with physical design teams on floor planning, timing closure, and DFT implementation
  • Perform full-chip integration and verification
  • Support chip bring-up, validation, and silicon debugging
  • Collaborate with algorithm and application engineers on image tuning, optimization, and qualification
  • Support silicon validation, debugging, and image quality tuning through production readiness
Minimum Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience
  • At least 2 years of hands-on experience designing RTL digital logic using Verilog/System Verilog, or equivalent industry experience
  • Proficiency with scripting languages such as Python or Perl to support design, verification, and automation workflows
  • Experience analyzing and optimizing area, power, and performance (PPA) trade-offs in digital designs
Preferred Qualifications
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related discipline
  • Strong background in image sensor and camera system design or integration
  • Experience with high-speed MIPI interfaces (e.g., CSI-2 / D-PHY / C-PHY)
  • Practical experience with Image Signal Processing (ISP) architectures and pipelines
Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on several factors such as relevant skills and experience, and the pay of employees in the similar role.
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