Title: Physical Design Engineer / Lead
Location: San Jose, CA
Job Description
- We are seeking an experienced Physical Design Engineer / Lead with 10+ years of experience in ASIC/SoC physical design. The ideal candidate will have hands-on expertise in the complete RTL-to-GDSII flow, including synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff for advanced technology nodes (5nm/3nm).
- Key Responsibilities
- Drive end-to-end physical design implementation from RTL to GDSII.
- Perform synthesis, floorplanning, place & route, CTS, routing, timing closure, and signoff.
- Implement low-power designs using UPF methodologies.
- Resolve SoC integration challenges, including SDC constraints and UPF.
- Develop automation scripts using TCL, Python, or Shell.
- Collaborate with cross-functional teams and lead/mentor engineers, including managing offshore teams.
Required Skills
- 10+ years of ASIC/SoC Physical Design experience.
- Hands-on experience with 5nm/3nm process nodes and successful tape-outs.
- Strong knowledge of RTL-to-GDSII implementation and timing closure.
- Experience with Innovus/ICC2, Design Compiler/Genus, PrimeTime, RedHawk/Voltus, and Calibre.
- Expertise in Floorplanning, Place & Route, CTS, STA, SDC, UPF, and Low-Power Design.
- Proficiency in TCL, Python, Perl, or Shell scripting.
- Must have experience leading and managing offshore teams.