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Asic Physical Design Engineer Jobs in California

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

Socionext US

Physical Design Engineer

Milpitas, CA · On-site

$195K - $220K/yr

Physical Design Engineer - Socionext America, Milpitas Description Socionext Inc. (SNI) is an ... Critical to this position is the ability to articulate technical discussions with ASIC Customers ...

Cisco

Senior ASIC Physical Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...

Cisco

Senior ASIC Physical Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...

Google

Senior ASIC Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full-chip Signoff teams. Additionally, you will solve technical problems with innovative ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

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All JobsAsic Physical Design Engineer JobsAsic Physical Design Engineer Jobs in California

Asic Physical Design Engineer information

See California salary details

$93.8K

$139.6K

How much do asic physical design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for asic physical design engineer in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, you need strong expertise in digital design, timing analysis, and semiconductor technology, often supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics for place-and-route, as well as relevant certifications in VLSI design, are highly valuable. Attention to detail, effective communication, and problem-solving abilities distinguish top professionals in this field. These competencies are crucial for ensuring accurate, efficient, and manufacturable ASIC designs in a fast-paced technological environment.

What are the typical daily responsibilities of an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, your daily tasks often include translating RTL designs into physical layouts, performing place-and-route, running static timing analysis, and optimizing power, performance, and area metrics. You will frequently collaborate with design, verification, and fabrication teams to address design challenges and ensure seamless integration of IP blocks. Regular project meetings, documentation of design processes, and participation in design reviews are also common. This role involves balancing technical precision with teamwork, making communication skills and adaptability essential for success.

What is an ASIC Physical Design Engineer?

An ASIC Physical Design Engineer is responsible for the back-end design and implementation of integrated circuits (ICs). They handle tasks such as floorplanning, placement, routing, timing closure, power optimization, and Design for Manufacturability (DFM). Using Electronic Design Automation (EDA) tools, they ensure the IC meets performance, power, and area (PPA) requirements. They collaborate with front-end design, verification, and fabrication teams to ensure a successful chip tape-out.

What are the most commonly searched types of Asic Physical Design Engineer jobs in California? The most popular types of Asic Physical Design Engineer jobs in California are:
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Asic Physical Design Engineer jobs near you
Infographic showing various Asic Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 70% Full Time, and 30% Contract. Highlights an 74% In-person, and 26% Remote job distribution, with an average salary of $137,583 per year, or $66.1 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Los Angeles, CA • On-site

$170K - $250K/yr

Full-time

Re-posted 12 days ago

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5–10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience with sign-off through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $170,000 – $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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