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Asic Physical Design Engineer Jobs in California

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

Socionext US

Physical Design Engineer

Milpitas, CA · On-site

$195K - $220K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Physical Design Engineer - Socionext America, Milpitas Description Socionext Inc. (SNI) is an ... Critical to this position is the ability to articulate technical discussions with ASIC Customers ...

Google

Senior ASIC Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full-chip Signoff teams. Additionally, you will solve technical problems with innovative ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

Meta

ASIC Engineer, Physical Design

Sunnyvale, CA

$178K/yr

ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff ...

MatX

ASIC/SOC Silicon Physical Design Engineer

Mountain View, CA · On-site

$175K - $362K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Minimum 8 years of industry experience in ASIC Physical Design * Great interpersonal and communication skills * Strong proficiency in programming languages such as Perl, Python, and TCL * Expertise ...

MatX

ASIC/SOC Silicon Physical Design Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Minimum 8 years of industry experience in ASIC Physical Design * Great interpersonal and communication skills * Strong proficiency in programming languages such as Perl, Python, and TCL * Expertise ...

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All JobsAsic Physical Design Engineer JobsAsic Physical Design Engineer Jobs in California

Asic Physical Design Engineer information

See California salary details

$93.8K

$139.6K

How much do asic physical design engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for asic physical design engineer in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, you need strong expertise in digital design, timing analysis, and semiconductor technology, often supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics for place-and-route, as well as relevant certifications in VLSI design, are highly valuable. Attention to detail, effective communication, and problem-solving abilities distinguish top professionals in this field. These competencies are crucial for ensuring accurate, efficient, and manufacturable ASIC designs in a fast-paced technological environment.

What are the typical daily responsibilities of an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, your daily tasks often include translating RTL designs into physical layouts, performing place-and-route, running static timing analysis, and optimizing power, performance, and area metrics. You will frequently collaborate with design, verification, and fabrication teams to address design challenges and ensure seamless integration of IP blocks. Regular project meetings, documentation of design processes, and participation in design reviews are also common. This role involves balancing technical precision with teamwork, making communication skills and adaptability essential for success.

What is an ASIC Physical Design Engineer?

An ASIC Physical Design Engineer is responsible for the back-end design and implementation of integrated circuits (ICs). They handle tasks such as floorplanning, placement, routing, timing closure, power optimization, and Design for Manufacturability (DFM). Using Electronic Design Automation (EDA) tools, they ensure the IC meets performance, power, and area (PPA) requirements. They collaborate with front-end design, verification, and fabrication teams to ensure a successful chip tape-out.

What are the most commonly searched types of Asic Physical Design Engineer jobs in California?

The most popular types of Asic Physical Design Engineer jobs in California are:

What are popular job titles related to Asic Physical Design Engineer jobs in California?

For Asic Physical Design Engineer jobs in California, the most frequently searched job titles are:

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Asic Physical Design Engineer jobs near you
Infographic showing various Asic Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 87% Full Time, and 13% Contract. Highlights an 88% In-person, and 12% Remote job distribution, with an average salary of $137,583 per year, or $66.1 per hour.

Senior ASIC physical design engineer

International Association of Plumbing and Mechanical Officials (IAPMO)

San Diego, CA • On-site

$150 - $210/hr

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Job description

Company Description

Eximietas Design is a leading technology consulting and solutions development company specializing in Chip Design, Firmware & Embedded Software, Cloud Computing, Cyber Security, and AI/ML. With an experienced engineering leadership team responsible for over 100+ successful chip tape-outs and numerous software solutions for global tech giants, Eximietas Design is committed to innovation and excellence. We deliver advanced solutions to help organizations excel in the rapidly evolving digital world. The company is ISO 9001 and ISO 27001 certified, with development centers in the United States and India.

Role Description

Are you ready to tape out the next beast chip? Join our team and turn complex constraints into clean GDSII.

Too many buffers in your life? Come optimize power, area, and performance with a team that values a clean design

We are hiring top-notch talent in ASIC Physical Design, 10+yrs, to grow with our team. Additional skills preferred: You have good background in SoC level/block timing closure, STA, Power analysis, Physical verification and EM/IR/ESD closure.

This is a full-time hybrid role for a Senior ASIC Physical Design Engineer based in San Jose or San Diego, CA, with flexibility for partial remote work. The incumbent will be responsible for leading ASIC physical design projects, including tasks such as floor planning, partitioning, clock tree synthesis, routing, timing closure, and design rule checking (DRC)/layout versus schematic (LVS) validation. The role also involves collaborating with cross-functional teams, ensuring the design aligns with specifications, and optimizing performance, power, and area parameters.

Qualifications
  • Strong expertise in Physical Design, including floor planning, implementation, STA timing closure, and verification.
  • Proficiency in RTL Design and RTL Coding, with experience in Verilog or VHDL.
  • Proven experience in Logic Design and Formal Verification techniques.
  • Solid understanding of timing analysis, congestion analysis, and power optimization.
  • Excellent problem-solving skills, attention to detail, and a high level of technical competence.
  • Strong communication and interpersonal skills, with the ability to work collaboratively across cross-functional teams.
  • Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with relevant hands-on experience.
  • Industry experience with successful ASIC design tape-outs is highly desirable.
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