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Asic Physical Design Engineer Jobs in California

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

Cisco

Senior ASIC Physical Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...

Google

Senior ASIC Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full-chip Signoff teams. Additionally, you will solve technical problems with innovative ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

Meta

ASIC Engineer, Physical Design

Sunnyvale, CA

$178K/yr

ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff ...

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All JobsAsic Physical Design Engineer JobsAsic Physical Design Engineer Jobs in California

Asic Physical Design Engineer information

See California salary details

$93.8K

$139.6K

How much do asic physical design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for asic physical design engineer in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, you need strong expertise in digital design, timing analysis, and semiconductor technology, often supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics for place-and-route, as well as relevant certifications in VLSI design, are highly valuable. Attention to detail, effective communication, and problem-solving abilities distinguish top professionals in this field. These competencies are crucial for ensuring accurate, efficient, and manufacturable ASIC designs in a fast-paced technological environment.

What are the typical daily responsibilities of an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, your daily tasks often include translating RTL designs into physical layouts, performing place-and-route, running static timing analysis, and optimizing power, performance, and area metrics. You will frequently collaborate with design, verification, and fabrication teams to address design challenges and ensure seamless integration of IP blocks. Regular project meetings, documentation of design processes, and participation in design reviews are also common. This role involves balancing technical precision with teamwork, making communication skills and adaptability essential for success.

What is an ASIC Physical Design Engineer?

An ASIC Physical Design Engineer is responsible for the back-end design and implementation of integrated circuits (ICs). They handle tasks such as floorplanning, placement, routing, timing closure, power optimization, and Design for Manufacturability (DFM). Using Electronic Design Automation (EDA) tools, they ensure the IC meets performance, power, and area (PPA) requirements. They collaborate with front-end design, verification, and fabrication teams to ensure a successful chip tape-out.

What are the most commonly searched types of Asic Physical Design Engineer jobs in California? The most popular types of Asic Physical Design Engineer jobs in California are:
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Asic Physical Design Engineer jobs near you
Infographic showing various Asic Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 70% Full Time, and 30% Contract. Highlights an 74% In-person, and 26% Remote job distribution, with an average salary of $137,583 per year, or $66.1 per hour.

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA Corporation

Santa Clara, CA • On-site

$136 - $218.50/hr

Other

Re-posted 3 days ago

Nvidia rating

9.6

Company rating: 9.6 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

8th of 242 rated software companies

Job description

Senior ASIC Physical Design Engineer, Netlisting

We are looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team.

What You'll Be Doing:
  • Drive physical design of high‑frequency and low‑power CPUs, GPUs, and SoCs at block level, cluster level, and or full chip level, focusing on netlist‑related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, and netlist quality checks.
  • Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.
What We Need to See:
  • BS (or equivalent experience in) Electrical or Computer Engineering with 5+ years’ experience, or MS (or equivalent experience) with 3+ years’ experience.
  • Expertise in logic equivalence checking/FV required from RTL to tape‑out with industry‑standard tools.
  • Deep understanding of hardware architecture and hands‑on skills in RTL/logic design for timing closure.
  • Experience in clock‑domain‑crossing checking and MTBF analysis, either with industry‑standard tools or in‑house tools.
  • Background with logic synthesis at either block or full‑chip level, at project execution and/or flow development.
  • Strong experience in full‑chip/sub‑chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
  • Expertise and in‑depth knowledge of industry‑standard EDA tools in related fields.
  • Proficiency in programming and scripting languages such as Perl, TCL, Make, Python, etc.
Ways to Stand Out from the Crowd:
  • Experience in logic synthesis and equivalence checking/FV.
  • Familiarity with industry tools and flow.
  • Strong hands‑on debugging capability and problem‑solving skills.
  • Background in DFT timing closure for various modes such as scan shift and capture, transition faults, BIST, etc.
  • Experience or strong drive to improve workflows and productivity through AI utilization.

Base salary range is $136,000 USD – $218,500 USD for Level3, and $168,000 USD – $264,500 USD for Level4. Equity and benefits are also available.

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

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What Nvidia employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

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About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993

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