SoC Design Engineer
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
SoC Design Engineer
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
SoC Design Engineer
Santa Clara, CA · On-site
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
Quick apply
SoC Design Engineer
Santa Clara, CA · On-site
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...
Design Verification Engineer-System Verilog/UVM
San Jose, CA · On-site
$95 - $120/hr
... engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and ...
Design Verification Engineer-System Verilog/UVM
San Jose, CA · On-site
$95 - $120/hr
... engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and ...
Senior FPGA Engineer - Verilog, Digital Logic Design
Austin, TX · On-site
$140K - $170K/yr
... RPGA engineering experience -Proven ability to write mathematical algorithms to run on a GPU in Windows -Previous experience using Verilog / SystemVerilog for digital logic design -Hands-on ...
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Senior FPGA Engineer - Verilog, Digital Logic Design
Austin, TX · On-site
$140K - $170K/yr
... RPGA engineering experience -Proven ability to write mathematical algorithms to run on a GPU in Windows -Previous experience using Verilog / SystemVerilog for digital logic design -Hands-on ...
Design Verification Engineer-System Verilog/UVM
San Jose, CA · On-site
$145K/yr
... engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and ...
Design Verification Engineer-System Verilog/UVM
San Jose, CA · On-site
$145K/yr
... engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and ...
Design Verification Engineer-System Verilog/UVM
San Jose, CA · Hybrid
$159K/yr
... engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and ...
Design Verification Engineer-System Verilog/UVM
San Jose, CA · Hybrid
$159K/yr
... engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and ...
Design Verification Engineer - Verification Lead - UVM / System Verilog / RTL Verification
Austin, TX · On-site
$70 - $80/hr
Job Title: Verification Lead - UVM / System Verilog / RTL Verification Location: 100% Onsite ... engineering professionals. This senior role provides an opportunity to take ownership of ...
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Design Verification Engineer - Verification Lead - UVM / System Verilog / RTL Verification
Austin, TX · On-site
$70 - $80/hr
Job Title: Verification Lead - UVM / System Verilog / RTL Verification Location: 100% Onsite ... engineering professionals. This senior role provides an opportunity to take ownership of ...
... programming skills including object oriented approaches Familiarity with revision control ... VHDL, Verilog, System verilog and OVM, Perl, C, Specman Tools: ModelSim (Questa), Specman
... programming skills including object oriented approaches Familiarity with revision control ... VHDL, Verilog, System verilog and OVM, Perl, C, Specman Tools: ModelSim (Questa), Specman
Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) (San Jose)
San Jose, CA · On-site
Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) We are looking for a Staff ML Engineer to lead fine-tuning and deployment of LLM‑based solutions for code/RTL workflows ...
Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) (San Jose)
San Jose, CA · On-site
Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) We are looking for a Staff ML Engineer to lead fine-tuning and deployment of LLM‑based solutions for code/RTL workflows ...
Quality Engineer
$120K - $125K/yr
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
Quality Engineer
$120K - $125K/yr
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
A technology services company is seeking a Machine Learning Engineer specializing in LLM fine-tuning for Verilog/RTL applications. This mid-senior level role requires significant experience in ML/AI ...
A technology services company is seeking a Machine Learning Engineer specializing in LLM fine-tuning for Verilog/RTL applications. This mid-senior level role requires significant experience in ML/AI ...
Quality Engineer
Santa Clara, CA · On-site
$120K - $125K/yr
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
Quality Engineer
Santa Clara, CA · On-site
$120K - $125K/yr
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
Quality Engineer
Santa Clara, CA · On-site
$120K - $125K/yr
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
Quality Engineer
Santa Clara, CA · On-site
$120K - $125K/yr
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
Staff Design and Verification Engineer, Pathfinding
Folsom, CA · On-site
$116 - $246/hr
Exposure to RTL verification, static timing analysis (STA), or timing-accurate Verilog. * Programming skills and Using Artificial Intelligence (AI) to verification/design workflow Job Profile(s ...
Staff Design and Verification Engineer, Pathfinding
Folsom, CA · On-site
$116 - $246/hr
Exposure to RTL verification, static timing analysis (STA), or timing-accurate Verilog. * Programming skills and Using Artificial Intelligence (AI) to verification/design workflow Job Profile(s ...
Quality Engineer
Santa Clara, CA · On-site
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
Quick apply
Quality Engineer
Santa Clara, CA · On-site
Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...
ASIC Design Engineer Technical Lead
$186K - $267K/yr
Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project tasks and problem solving.
ASIC Design Engineer Technical Lead
$186K - $267K/yr
Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project tasks and problem solving.
ASIC Design Engineer Technical Lead
San Jose, CA · On-site
$186K - $267K/yr
Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project tasks and problem solving.
ASIC Design Engineer Technical Lead
San Jose, CA · On-site
$186K - $267K/yr
Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project tasks and problem solving.
Principal Firmware Engineer
Eden Prairie, MN · On-site
$140 - $210/hr
VHDL experience preferred, Verilog experience acceptable. This is in addition to having in‑depth ... Applies sound engineering principles in the development of digital design/architecture for the ...
Principal Firmware Engineer
Eden Prairie, MN · On-site
$140 - $210/hr
VHDL experience preferred, Verilog experience acceptable. This is in addition to having in‑depth ... Applies sound engineering principles in the development of digital design/architecture for the ...
Verilog Engineer information
See salary details
$39K - $48K
3% of jobs
$48K - $56.9K
3% of jobs
$56.9K - $65.9K
4% of jobs
$65.9K - $74.8K
7% of jobs
$74.8K - $83.8K
6% of jobs
$84.5K is the 25th percentile. Wages below this are outliers.
$83.8K - $92.7K
6% of jobs
The median wage is $100.8K / yr.
$92.7K - $101.7K
21% of jobs
$101.7K - $110.6K
4% of jobs
$116.4K is the 75th percentile. Wages above this are outliers.
$110.6K - $119.6K
29% of jobs
$119.6K - $128.5K
2% of jobs
$128.5K - $137.5K
13% of jobs
$39K
$101.8K
$137.5K
How much do verilog engineer jobs pay per year?
As of Aug 28, 2026, the average yearly pay for verilog engineer in the United States is $101,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $116,500.00 per year, depending on experience, location, and employer.
What is a Verilog engineer?
A Verilog Engineer is a hardware design professional who specializes in using the Verilog hardware description language (HDL) to design, simulate, and verify digital circuits. They work on developing FPGA and ASIC designs for applications in industries such as telecommunications, automotive, and consumer electronics. Their role often includes writing Verilog code, running simulations, debugging hardware issues, and optimizing performance. They collaborate with systems engineers and verification teams to ensure the correctness and efficiency of digital designs.
What are the typical daily responsibilities of a Verilog engineer?
A Verilog Engineer typically spends their day writing and verifying Verilog code to design and simulate digital logic circuits for ASICs or FPGAs. Their responsibilities include reviewing design specifications, collaborating with hardware and software teams, performing code reviews, and troubleshooting issues found during simulation or synthesis. They also document their work and may assist in optimizing designs for performance or resource utilization. Effective communication and teamwork are important, as Verilog Engineers often work closely with cross-functional engineering teams throughout the development cycle.
What are the key skills and qualifications needed to thrive in the Verilog engineer position, and why are they important?
To thrive as a Verilog Engineer, you need strong proficiency in digital design principles, solid experience with hardware description languages (HDLs) like Verilog, and usually a degree in electrical engineering or a related field. Familiarity with ASIC/FPGA design tools such as ModelSim, Synopsys, or Xilinx Vivado, and certifications in FPGA or hardware design can be advantageous. Attention to detail, strong problem-solving skills, and effective teamwork and communication abilities distinguish top performers in this role. These skills and qualities are crucial to efficiently designing, verifying, and delivering high-performance digital systems that meet project requirements and deadlines.
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Job description
Job Title: SoC Design Engineer
Job Duties:
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP design, analysis, integration, and validation. Collaborate with physical design teams on floor-planning, timing closure, and DFT implementation. Conduct timing control logic design and static timing analysis (STA) for sensor interfaces and mixed-signal integration. Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline according to PRD/design specification and system architecture of SoC products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc. Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital and analog engineers for system design, integration and validation. Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation. Work with algorithm and application engineers for project-based microarchitecture improvements. Conduct silicon validation, debugging and tuning.
Requirements:
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field.
Required skills and/or academic training in the following:
- Arithmetic circuit design related to general datapath circuits, ML and AI circuits.
- Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and debug.
- Design and design debug with System Verilog; Logic design and analysis.
- Processing Subsystem, including superscalar out-of-order cores, multicore and heterogeneous processors, and purpose-specific accelerators.
- Design tools, such as microarchitecture simulators, RTL synthesis tools, and modeling for area, power, and thermal.
- FPGA platforms to compute acceleration.
- FPGAs technology, architecture and applications.
- Register-Transfer Level (RTL) hardware design.
- Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks.
- Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal chip design.
- Full-chip integration and verification for tapeout.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
About Omnivision Technologies
Sourced by ZipRecruiter
Industry
Software development
Company size
1,001 - 5,000 Employees
Headquarters location
Santa Clara, CA, US
Year founded
1995