Senior FPGA Engineer #2730
$106K - $197K/yr
Senior FPGA Engineer ... Please apply ONLY if you have extensive FPGA and Verilog experience United States Citizenship is ...
$106K - $197K/yr
Senior FPGA Engineer ... Please apply ONLY if you have extensive FPGA and Verilog experience United States Citizenship is ...
$106K - $197K/yr
Senior FPGA Engineer ... Please apply ONLY if you have extensive FPGA and Verilog experience United States Citizenship is ...
Specialist, FPGA/ASIC Hardware Engineer, Electrical Engineering Job Code: 37369 Job Location ... Developing Verilog HDL targeting Antifuse and enhanced Flash FPGA's. * Performing effective ...
Specialist, FPGA/ASIC Hardware Engineer, Electrical Engineering Job Code: 37369 Job Location ... Developing Verilog HDL targeting Antifuse and enhanced Flash FPGA's. * Performing effective ...
Santa Clara, CA · On-site
$151K - $194K/yr
FPGA Verification Engineer Location: Santa Clara, CA-Onsite 100%, Day 1 Mon-Fri Duration: 12 ... Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard ...
Santa Clara, CA · On-site
$151K - $194K/yr
FPGA Verification Engineer Location: Santa Clara, CA-Onsite 100%, Day 1 Mon-Fri Duration: 12 ... Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in Perl or Python Preferred Qualifications Master's degree preferred In depth ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in Perl or Python Preferred Qualifications Master's degree preferred In depth ...
Sunnyvale, CA · On-site
$161K - $197K/yr
Verilog, System Verilog, C/C++ based verification, and UVM methodology Description: · We are seeking a talented and experienced Design Verification Engineer to join our dynamic team. The ideal ...
New
Sunnyvale, CA · On-site
$161K - $197K/yr
Verilog, System Verilog, C/C++ based verification, and UVM methodology Description: · We are seeking a talented and experienced Design Verification Engineer to join our dynamic team. The ideal ...
New
Staff/Sr. Engineer (Verification) Requisition No.: 6200-1023 Type of Position: Regular, Exempt ... Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL ...
Staff/Sr. Engineer (Verification) Requisition No.: 6200-1023 Type of Position: Regular, Exempt ... Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL ...
San Jose, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to ... using HDL (Verilog/ System Verilog). • Perform synthesis, timing analysis, Lint, formal ...
San Jose, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to ... using HDL (Verilog/ System Verilog). • Perform synthesis, timing analysis, Lint, formal ...
Austin, TX · On-site
$128K - $165K/yr
FPGA Engineer Engineer (eInfochips) Location: San Jose CA and Austin TX (Day-1 Onsite) Experience ... Proficient in Verilog/System Verilog coding constructs. * Knowledge of front-end tools (Verilog ...
Austin, TX · On-site
$128K - $165K/yr
FPGA Engineer Engineer (eInfochips) Location: San Jose CA and Austin TX (Day-1 Onsite) Experience ... Proficient in Verilog/System Verilog coding constructs. * Knowledge of front-end tools (Verilog ...
Cupertino, CA · On-site
$167K/yr
... verification engineers.Formal tools like LINT, CDC,RDC will be used to guarantee RTL quality ... Verilog and System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm ...
Cupertino, CA · On-site
$167K/yr
... verification engineers.Formal tools like LINT, CDC,RDC will be used to guarantee RTL quality ... Verilog and System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in Perl or Python Preferred Qualifications Master's degree preferred In depth ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in Perl or Python Preferred Qualifications Master's degree preferred In depth ...
$135K - $170K/yr
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize andoptimize RTL for timing, area, and power. * Explore ...
$135K - $170K/yr
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize andoptimize RTL for timing, area, and power. * Explore ...
Fort George G Meade, MD · On-site
$137K - $180K/yr
> Hardware/Software System Engineer (All Levels) Fuse Engineering LLC Hardware/Software System ... Develop and simulate HDL code (VHDL or Verilog) using ModelSim or equivalent tools. * Utilize ...
Fort George G Meade, MD · On-site
$137K - $180K/yr
> Hardware/Software System Engineer (All Levels) Fuse Engineering LLC Hardware/Software System ... Develop and simulate HDL code (VHDL or Verilog) using ModelSim or equivalent tools. * Utilize ...
Description We are seeking an experienced Hardware/Software Engineer to join our team, specializing ... Develop and simulate HDL code (VHDL or Verilog) using ModelSim or equivalent tools. * Utilize ...
Description We are seeking an experienced Hardware/Software Engineer to join our team, specializing ... Develop and simulate HDL code (VHDL or Verilog) using ModelSim or equivalent tools. * Utilize ...
San Jose, CA · On-site
$152K - $195K/yr
FPGA Engineer Engineer (eInfochips) Location: San Jose CA and Austin TX (Day-1 Onsite) Experience ... Proficient in Verilog/System Verilog coding constructs. * Knowledge of front-end tools (Verilog ...
San Jose, CA · On-site
$152K - $195K/yr
FPGA Engineer Engineer (eInfochips) Location: San Jose CA and Austin TX (Day-1 Onsite) Experience ... Proficient in Verilog/System Verilog coding constructs. * Knowledge of front-end tools (Verilog ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in scripting languages such as Perl or Python Preferred Qualifications Master ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in scripting languages such as Perl or Python Preferred Qualifications Master ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in scripting languages such as Perl or Python Preferred Qualifications Master ...
Santa Clara, CA · On-site
$159K/yr
... Verilog, or vectors according to test plans to drive testing in simulation and emulation ... Programming skills in scripting languages such as Perl or Python Preferred Qualifications Master ...
San Jose, CA · Hybrid
$159K - $195K/yr
You thrive in a collaborative engineering environment and enjoy solving complex technical ... Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar ...
San Jose, CA · Hybrid
$159K - $195K/yr
You thrive in a collaborative engineering environment and enjoy solving complex technical ... Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar ...
$134K - $164K/yr
Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness ... Keen engineering problem solving skills and a mind for seeking innovative solutions to reduce ...
$134K - $164K/yr
Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness ... Keen engineering problem solving skills and a mind for seeking innovative solutions to reduce ...
Santa Clara, CA · On-site
$159K/yr
Description As a CPU Processor Power Management Verification Engineer, you will have the ... Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and ...
Santa Clara, CA · On-site
$159K/yr
Description As a CPU Processor Power Management Verification Engineer, you will have the ... Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and ...
New York, NY · On-site
$114K - $157K/yr
Verify designs written in VHDL and support verification using Verilog/SystemVerilog. * Debug FPGA issues and collaborate with cross-functional engineering teams. * Work with Xilinx Vivado tools and ...
Quick apply
New York, NY · On-site
$114K - $157K/yr
Verify designs written in VHDL and support verification using Verilog/SystemVerilog. * Debug FPGA issues and collaborate with cross-functional engineering teams. * Work with Xilinx Vivado tools and ...
$39K - $48K
3% of jobs
$48K - $56.9K
3% of jobs
$56.9K - $65.9K
4% of jobs
$65.9K - $74.8K
7% of jobs
$74.8K - $83.8K
6% of jobs
$84.5K is the 25th percentile. Wages below this are outliers.
$83.8K - $92.7K
6% of jobs
The median wage is $100.8K / yr.
$92.7K - $101.7K
21% of jobs
$101.7K - $110.6K
4% of jobs
$116.4K is the 75th percentile. Wages above this are outliers.
$110.6K - $119.6K
29% of jobs
$119.6K - $128.5K
2% of jobs
$128.5K - $137.5K
13% of jobs
$39K
$101.8K
$137.5K
A Verilog Engineer is a hardware design professional who specializes in using the Verilog hardware description language (HDL) to design, simulate, and verify digital circuits. They work on developing FPGA and ASIC designs for applications in industries such as telecommunications, automotive, and consumer electronics. Their role often includes writing Verilog code, running simulations, debugging hardware issues, and optimizing performance. They collaborate with systems engineers and verification teams to ensure the correctness and efficiency of digital designs.
To thrive as a Verilog Engineer, you need strong proficiency in digital design principles, solid experience with hardware description languages (HDLs) like Verilog, and usually a degree in electrical engineering or a related field. Familiarity with ASIC/FPGA design tools such as ModelSim, Synopsys, or Xilinx Vivado, and certifications in FPGA or hardware design can be advantageous. Attention to detail, strong problem-solving skills, and effective teamwork and communication abilities distinguish top performers in this role. These skills and qualities are crucial to efficiently designing, verifying, and delivering high-performance digital systems that meet project requirements and deadlines.
A Verilog Engineer typically spends their day writing and verifying Verilog code to design and simulate digital logic circuits for ASICs or FPGAs. Their responsibilities include reviewing design specifications, collaborating with hardware and software teams, performing code reviews, and troubleshooting issues found during simulation or synthesis. They also document their work and may assist in optimizing designs for performance or resource utilization. Effective communication and teamwork are important, as Verilog Engineers often work closely with cross-functional engineering teams throughout the development cycle.

$106K - $197K/yr
Full-time
Re-posted 13 days ago
Sourced by ZipRecruiter
Recruiting and staffing services
11 - 50 Employees
Simi Valley, CA, US
1987