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Verilog Engineer Jobs (NOW HIRING)

Superbeo

Design Verification Lead Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions ... Exposure to FPGA programming and FPGA tools will be helpful. * Independent, self-motivated with ...

Lancesoft

Test Engineer 1

San Jose, CA · On-site

$45 - $57.97/hr

Key skills are software (System Verilog, C/C++, object oriented programming, scripting (e.G. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.

Ambarella

$135K - $170K/yr

Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize andoptimize RTL for timing, area, and power. * Explore ...

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114.30K - $157K/yr

Verify designs written in VHDL and support verification using Verilog/SystemVerilog. * Debug FPGA issues and collaborate with cross-functional engineering teams. * Work with Xilinx Vivado tools and ...

Cisco

ASIC Design Technical Lead

San Jose, CA

$183.80K - $263.60K/yr

Verilog/System Verilog programming experience. * Interactive and waveform debug experience. * Experience resolving setup and hold timing violations with RTL modification. * Experience developing ...

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How much do verilog engineer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for verilog engineer in the United States is $101,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $116,500.00 per year, depending on experience, location, and employer.

What is a Verilog Engineer job?

A Verilog Engineer is a hardware design professional who specializes in using the Verilog hardware description language (HDL) to design, simulate, and verify digital circuits. They work on developing FPGA and ASIC designs for applications in industries such as telecommunications, automotive, and consumer electronics. Their role often includes writing Verilog code, running simulations, debugging hardware issues, and optimizing performance. They collaborate with systems engineers and verification teams to ensure the correctness and efficiency of digital designs.

What are the key skills and qualifications needed to thrive in the Verilog Engineer position, and why are they important?

To thrive as a Verilog Engineer, you need strong proficiency in digital design principles, solid experience with hardware description languages (HDLs) like Verilog, and usually a degree in electrical engineering or a related field. Familiarity with ASIC/FPGA design tools such as ModelSim, Synopsys, or Xilinx Vivado, and certifications in FPGA or hardware design can be advantageous. Attention to detail, strong problem-solving skills, and effective teamwork and communication abilities distinguish top performers in this role. These skills and qualities are crucial to efficiently designing, verifying, and delivering high-performance digital systems that meet project requirements and deadlines.

What are the typical daily responsibilities of a Verilog Engineer?

A Verilog Engineer typically spends their day writing and verifying Verilog code to design and simulate digital logic circuits for ASICs or FPGAs. Their responsibilities include reviewing design specifications, collaborating with hardware and software teams, performing code reviews, and troubleshooting issues found during simulation or synthesis. They also document their work and may assist in optimizing designs for performance or resource utilization. Effective communication and teamwork are important, as Verilog Engineers often work closely with cross-functional engineering teams throughout the development cycle.
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Verilog Engineer jobs near you
Infographic showing various Verilog Engineer job openings in the United States as of May 2026, with employment types broken down into 96% Full Time, and 4% Part Time. Highlights an 6% Physical, 29% Hybrid, and 65% Remote job distribution, with an average salary of $101,752 per year, or $48.9 per hour.
(6200-1023) Staff/Sr. Engineer (Verification)

(6200-1023) Staff/Sr. Engineer (Verification)

Achronix Semiconductor Corporation

Santa Clara, CA • On-site

Full-time

Posted 25 days ago

Job description

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Position Profile Name: Staff/Sr. Engineer (Verification)
Requisition No.:6200-1023
Type of Position:Regular, Exempt
Reports to:Hardware Engineering Manager, Core Technology
Location:Santa Clara, California
Contact:hr@achronix.com
Job Description/Responsibilities
The successful candidate will be responsible for the functional verification of high-performance digital logic for standalone and embedded FPGAs.
Responsibilities include the following:
  • Define the test plan and setup the verification environment at unit and chip level
  • Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL functionality
  • Run functional simulations and regressions, including gate level and timing annotated simulations
  • Debug issues, report and track bugs to closure
  • Collect coverage metrics and track verification progress
  • Support porting of the verification infrastructure for post-silicon validation
  • Mentor junior engineers
Required Skills and Qualifications
  • Experience designing/maintaining flows and methodologies from scratch
  • Experience with digital VLSI design and verification
  • Proficiency in Verilog coding and using a scripting language (e.g., Python or Perl) is a must
  • Experience with Simulation, Debugging and Formal Verification
  • Experience with UVM or System Verilog for verification is a plus
  • Familiarity with using and/or designing FPGAs is a plus
  • Familiarity with revision-control systems (e.g., perforce, git) is a plus
  • Excellent debugging skills
  • Well organized and excellent communication skills
  • BS/MS in Electrical Engineering or Computer Science + 2-10 years' experience

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