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Verilog Engineer Jobs (NOW HIRING)

Glow Networks

Principal Verification Engineer

Dallas, TX · On-site

$127K/yr

The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with ...

WILLCOR Inc

Systems Engineer (VHDL)

Glen Burnie, MD

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

WILLCOR, Inc.

Systems Engineer (VHDL)

Glen Burnie, MD · On-site

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

Ambarella

Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.

Full Scope

Systems Engineer (VHDL)

Glen Burnie, MD · On-site

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full-Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

CivicMinds, Inc.

ASIC Design Engineer

San Diego, CA · On-site

Creating a constrained-random verification environment using System Verilog and UVM * Identifying ... Debugging tests with design engineers to deliver functionally correct design blocks * Closing ...

WILLCOR Inc

Systems Engineer (Hardware)

Glen Burnie, MD

$119K - $157K/yr

Systems Engineer (Hardware) Location: Linthicum, MD Required Clearance : TS/SCI w/ CI Poly Salary ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

WILLCOR, Inc.

Systems Engineer (Hardware)

Glen Burnie, MD · On-site

$119K - $157K/yr

Systems Engineer (Hardware) Location: Linthicum, MD Required Clearance : TS/SCI w/ CI Poly Salary ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

WILLCOR Inc

Systems Engineer (Hardware)

Glen Burnie, MD

$119K - $157K/yr

Systems Engineer (Hardware) Location: Linthicum, MD Required Clearance : TS/SCI w/ CI Poly Salary ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

Distro

Hardware Engineer

Cincinnati, OH

$120K - $160K/yr

The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ... Programming experience in C for embedded systems, including development of algorithms, manipulation ...

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How much do verilog engineer jobs pay per year?

As of Jun 27, 2026, the average yearly pay for verilog engineer in the United States is $101,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $116,500.00 per year, depending on experience, location, and employer.

What is a Verilog Engineer job?

A Verilog Engineer is a hardware design professional who specializes in using the Verilog hardware description language (HDL) to design, simulate, and verify digital circuits. They work on developing FPGA and ASIC designs for applications in industries such as telecommunications, automotive, and consumer electronics. Their role often includes writing Verilog code, running simulations, debugging hardware issues, and optimizing performance. They collaborate with systems engineers and verification teams to ensure the correctness and efficiency of digital designs.

What are the key skills and qualifications needed to thrive in the Verilog Engineer position, and why are they important?

To thrive as a Verilog Engineer, you need strong proficiency in digital design principles, solid experience with hardware description languages (HDLs) like Verilog, and usually a degree in electrical engineering or a related field. Familiarity with ASIC/FPGA design tools such as ModelSim, Synopsys, or Xilinx Vivado, and certifications in FPGA or hardware design can be advantageous. Attention to detail, strong problem-solving skills, and effective teamwork and communication abilities distinguish top performers in this role. These skills and qualities are crucial to efficiently designing, verifying, and delivering high-performance digital systems that meet project requirements and deadlines.

What are the typical daily responsibilities of a Verilog Engineer?

A Verilog Engineer typically spends their day writing and verifying Verilog code to design and simulate digital logic circuits for ASICs or FPGAs. Their responsibilities include reviewing design specifications, collaborating with hardware and software teams, performing code reviews, and troubleshooting issues found during simulation or synthesis. They also document their work and may assist in optimizing designs for performance or resource utilization. Effective communication and teamwork are important, as Verilog Engineers often work closely with cross-functional engineering teams throughout the development cycle.

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Verilog Engineer jobs near you
Principal Verification Engineer

Principal Verification Engineer

Glow Networks

Dallas, TX • On-site

$127K/yr

Full-time

Posted 22 days ago

Job description

**Job Summary:**
The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. They must develop test plans and coverage metrics, create scripts to automate verification processes, perform failure analysis of simulations, and collaborate with design engineers to resolve issues.
**Qualifications:**
- 7+ years of experience in pre-silicon design verification.
- Proficiency in C-shell scripting, Verilog-HDL, and System Verilog.
- Strong knowledge in SV Assertions, UVM/OVM, and functional code coverage.
- Experience with advanced peripheral bus Verification IPs (e.g., GPIO, UART, SPI, SW, JTAG, I2C).
- Proficient with Cadence tools like NC Verilog, NCSIM, and Simvision. Experience with linting tools such as Spyglass is beneficial.
- Independent, self-motivated, with excellent analytical and communication skills.
**Responsibilities:**
- Architect and create verification environments using System-Verilog and UVM IPs for IPs and SoCs.
- Develop test plans and coverage metrics, and write block and chip-level tests based on specifications.
- Utilize PERL/Python scripts to automate verification processes and debug.
- Conduct failure analysis of Register Transfer Level and Gate simulations, collaborating with design engineers for resolution.
- Work with architects to define simulation use-case scenarios.

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