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Vivado Hls Jobs (NOW HIRING)

ICEYE US

Firmware Engineer

Irvine, CA · On-site

$145 - $175/hr

  • Medical

  • PTO

... Vivado HLS) * At least 3-5 years demonstrated experience with digital signal processing implementation in FPGA fabric (filtering, FFTs, digital down‑conversion, waveform generation) * 3-5 years ...

ICEYE US-SkyFi

Firmware Engineer

Irvine, CA · On-site

$145 - $175/hr

  • Medical

  • PTO

... Vivado HLS) * 3+ years demonstrated experience with digital signal processing implementation in FPGA fabric (filtering, FFTs, digital down-conversion, waveform generation) * 3+ years hands‑on ...

Encode

FPGA Engineer with Security Clearance

Camden, NJ · On-site

$131K - $168K/yr

... Xilinx/Vivado expertise, revision control experience, and a STEM degree. Preferred skills include C++, Ethernet/TCP-IP/PCIe protocols, Xilinx SoC, PetaLinux, and HLS. Strong communication and ...

Next Matter

Senior FPGA Engineer

Allen, TX · On-site

$90 - $130/hr

  • Medical

  • Dental

  • Vision

  • PTO

Experience optimizing HLS pipelines for latency, parallelism, and memory bandwidth * Familiarity with AXI interfaces, DMA, and FPGA-based accelerators * Experience with Vivado and Vitis development ...

Booz Allen Hamilton, Inc.

Embedded FPGA Engineer

Mclean, VA · On-site

$131K - $168K/yr

  • Medical

  • Life

  • Retirement

  • PTO

... or HLS along with evaluation tools such as simulation, synthesis, fitting, timing analysis, implementation, and debug * Experience with Xilinx, Vitis, Vivado or FPGA development ecosystems and ...

Chipton Ross

FPGA/ASIC Design Engineer

Camden, NJ · On-site

$125/hr

PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE) High Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP) and System Verilog Assertions (SVA). Knowledge of high-speed protocols (PCIe, TCP/IP ...

Booz Allen Hamilton, Inc.

Embedded FPGA Engineer

Mclean, VA · On-site +1

  • Medical

  • Life

  • Retirement

  • PTO

... or HLS along with evaluation tools such as simulation, synthesis, fitting, timing analysis, implementation, and debug * Experience with Xilinx, Vitis, Vivado or FPGA development ecosystems and ...

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Vivado Hls information

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How much do vivado hls jobs pay per year?

As of Aug 17, 2026, the average yearly pay for vivado hls in the United States is $94,437.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,500.00 and $105,500.00 per year, depending on experience, location, and employer.

What is Vivado HLS?

Vivado HLS (High-Level Synthesis) is a tool developed by Xilinx that allows designers to compile C, C++, or SystemC code into hardware description language (HDL) such as Verilog or VHDL. This process enables faster design cycles for FPGA and ASIC development by allowing engineers to describe hardware behavior using high-level programming languages instead of traditional RTL coding. Vivado HLS is widely used in applications that require rapid prototyping, algorithm acceleration, and design optimization for programmable logic devices.

What skills and qualifications are needed to thrive as a Vivado HLS engineer?

To thrive as a Vivado HLS Engineer, you need a solid background in digital design, C/C++ programming, and FPGA development, often supported by a degree in electrical engineering or related fields. Proficiency with Xilinx Vivado HLS tools, simulation environments, and hardware description languages like VHDL or Verilog is essential. Strong analytical thinking, attention to detail, and effective problem-solving set outstanding engineers apart. These skills ensure efficient translation of algorithms into hardware, optimized FPGA implementations, and successful project outcomes.

What are common challenges engineers face when using Vivado HLS in FPGA development projects?

Engineers working with Vivado HLS often encounter challenges related to optimizing C/C++ code for hardware synthesis, such as balancing resource utilization with performance goals. Understanding how high-level code translates to hardware structures can require a learning curve, especially when debugging timing issues or unexpected synthesis results. Collaboration with RTL engineers and system architects is common, as integration with existing IP and meeting overall system constraints are key aspects of the workflow. Regular review and iteration are typically required to achieve the desired hardware efficiency.

What is Vivado HLS used for?

Vivado HLS (High-Level Synthesis) is used by FPGA design engineers to convert C, C++, and SystemC code into hardware description language (HDL) such as VHDL or Verilog. It streamlines the development process by enabling high-level algorithm modeling and automatic hardware generation, facilitating faster prototyping and implementation of FPGA-based systems.
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Vivado Hls jobs near you
Infographic showing various Vivado Hls job openings in the United States as of August 2026, with employment types broken down into 70% Full Time, and 30% Contract. Highlights an 90% In-person, and 10% Remote job distribution, with an average salary of $94,437 per year, or $45.4 per hour.

FPGA/ASIC Design Engineer (Secret) - Reston, VA - 5137

Altimeter Solutions

Reston, VA • On-site

$128K - $176K/yr

Contractor

Re-posted 12 days ago

Job description

We've determined which skillsets are most beneficial for this role. These skills are listed first below as the Must Haves and Nice to Haves our hiring team highly prefers. Below that you'll find the standard job description for this opportunity.
Must Haves:
  • Bachelor's degree in electrical engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Master's Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
  • Possess an active SECRET Clearance
  • Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
  • Proficient in VHDL design process and FPGA flow
  • Knowledge of Ethernet, TCP/IP protocols
  • Strong logic/board debug, and analytical skills.
  • Excellent written, verbal, and presentation skills.
  • A PLUS for prior experience with:
  • High Level Synthesis (HLS) with Vivado,
  • Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
  • Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
  • VHDL Experience is required for all candidates to be considered.
  • Looking for mid-senior level folks
  • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
  • Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
  • Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
  • Mentor EDA CDC/Lint/AC/RDC
  • Derive engineering specifications from system requirements and develop detailed architecture
  • Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
  • Generate test plans
  • Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
  • Silicon/FPGA bring up, characterization and production ramp/support/collateral

Nice to Haves:
  • Prior experience in Aerospace / Defense
  • Experience in C++ (OOP)
  • Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
  • Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
  • Experience with Universal Verification Mythology (UVM)
  • Experience with project leadership and EVM

Job Description:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
Our company has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Please see our website for more job openings: https://altimetersolutions.com/altimeter-solutions-job-board/

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