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Vivado Hls Jobs (NOW HIRING)

Booz Allen Hamilton

Embedded FPGA Engineer

Mclean, VA · On-site

$131K - $168K/yr

... or HLS along with evaluation tools such as simulation, synthesis, fitting, timing analysis, implementation, and debug * Experience with Xilinx, Vitis, Vivado or FPGA development ecosystems and ...

Long Wall

FPGA Design Engineer

Long Beach, CA · On-site

$135K - $225K/yr

Experience with Xilinx Vivado design suite for synthesis, implementation, and debugging ... Experience with Xilinx High-Level Synthesis (HLS) for algorithm acceleration * Experience with ...

Long Wall

FPGA Design Engineer

Long Beach, CA · On-site

$129K - $178K/yr

Experience with Xilinx Vivado design suite for synthesis, implementation, and debugging ... Experience with Xilinx High-Level Synthesis (HLS) for algorithm acceleration * Experience with ...

Long Wall

FPGA Design Engineer

Long Beach, CA · On-site

$129K - $178K/yr

Experience with Xilinx Vivado design suite for synthesis, implementation, and debugging ... Experience with Xilinx High-Level Synthesis (HLS) for algorithm acceleration * Experience with ...

Long Wall

FPGA Design Engineer

Long Beach, CA · On-site

$129K - $178K/yr

Experience with Xilinx Vivado design suite for synthesis, implementation, and debugging ... Experience with Xilinx High-Level Synthesis (HLS) for algorithm acceleration * Experience with ...

Prattwhitney

Principal FPGA Engineer

Mckinney, TX · On-site

$107.50 - $204.50/hr

... AMD Vivado, Altera Quartus Prime Pro, or Libero. * Generate FPGA designs for gigabit and ... Experience with High Level Synthesis (HLS), vector processors and/or GPUs, and using AI to improve ...

Raytheon Technologies

Principal FPGA Engineer

Fort Wayne, IN · On-site

$137K - $167K/yr

AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Using ...

Raytheon

Senior FPGA Design Engineer

Fort Wayne, IN

$121K - $167K/yr

AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs

Raytheon Technologies

Principal FPGA Engineer

Mckinney, TX · On-site

$129K - $157K/yr

... AMD Vivado, Altera Quartus Prime Pro or Libero. * Generate FPGA designs for the following ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Using ...

L3HHCM20

Lead, Software Engineer - FPGA

Salt Lake City, UT · On-site

$124K - $160K/yr

... Xilinx Vivado/ISE, and/or Intel Quartus * Experience with high-speed serial FPGA interfaces ... Experience with high-level synthesis (HLS) * Hands-on laboratory debug experience using signal ...

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Vivado Hls information

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How much do vivado hls jobs pay per year?

As of Aug 18, 2026, the average yearly pay for vivado hls in the United States is $94,437.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,500.00 and $105,500.00 per year, depending on experience, location, and employer.

What is Vivado HLS?

Vivado HLS (High-Level Synthesis) is a tool developed by Xilinx that allows designers to compile C, C++, or SystemC code into hardware description language (HDL) such as Verilog or VHDL. This process enables faster design cycles for FPGA and ASIC development by allowing engineers to describe hardware behavior using high-level programming languages instead of traditional RTL coding. Vivado HLS is widely used in applications that require rapid prototyping, algorithm acceleration, and design optimization for programmable logic devices.

What skills and qualifications are needed to thrive as a Vivado HLS engineer?

To thrive as a Vivado HLS Engineer, you need a solid background in digital design, C/C++ programming, and FPGA development, often supported by a degree in electrical engineering or related fields. Proficiency with Xilinx Vivado HLS tools, simulation environments, and hardware description languages like VHDL or Verilog is essential. Strong analytical thinking, attention to detail, and effective problem-solving set outstanding engineers apart. These skills ensure efficient translation of algorithms into hardware, optimized FPGA implementations, and successful project outcomes.

What are common challenges engineers face when using Vivado HLS in FPGA development projects?

Engineers working with Vivado HLS often encounter challenges related to optimizing C/C++ code for hardware synthesis, such as balancing resource utilization with performance goals. Understanding how high-level code translates to hardware structures can require a learning curve, especially when debugging timing issues or unexpected synthesis results. Collaboration with RTL engineers and system architects is common, as integration with existing IP and meeting overall system constraints are key aspects of the workflow. Regular review and iteration are typically required to achieve the desired hardware efficiency.

What is Vivado HLS used for?

Vivado HLS (High-Level Synthesis) is used by FPGA design engineers to convert C, C++, and SystemC code into hardware description language (HDL) such as VHDL or Verilog. It streamlines the development process by enabling high-level algorithm modeling and automatic hardware generation, facilitating faster prototyping and implementation of FPGA-based systems.
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Vivado Hls jobs near you
Infographic showing various Vivado Hls job openings in the United States as of August 2026, with employment types broken down into 70% Full Time, and 30% Contract. Highlights an 90% In-person, and 10% Remote job distribution, with an average salary of $94,437 per year, or $45.4 per hour.

(7820-1002) Architect

Achronix Semiconductor Corporation

Santa Clara, CA • On-site

Full-time

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Position Profile Name:Architect
Requisition No.:7820-1002
Type of Position:Regular, Exempt
Reports to:VP Chief Technologist
Department:
Mktg - Tech. Ecosystems
Location:
Santa Clara, CA
Contact:hr@achronix.com
Job Description/Responsibilities
The Technology Ecosystems group at Achronix is looking for an all-around, broadly-oriented, hands-on architect to be a highly-motivated team member making an impact by establishing Achronix FPGA products as the most compelling solution to customer requirements across a wide variety of disciplines, including HPC, AI/ML and HLS. Achronix focuses on high-performance FPGA solutions in the form of stand-alone FPGAs, embedded FPGAs and chiplets, manufactured in a variety of technology nodes ranging from modern to cutting-edge. A central focus of this position is to identify where Achronix products can win, and to understand customer concerns to further improve Achronix products to solve customer problems.
Achronix is known for having delivered many industry firsts:
  • The first to deliver FPGAs with hardened protocol controllers
  • The first to deliver FinFET FPGAs
  • The first to successfully deploy embedded FPGA IP
  • The first to release a highly integrated design flow
  • The first to launch the MLP feature
  • The first to deliver the highly-integrated 2D NoC in the fabric to harden data transport
Primary Job Responsibilities
  • Conceive, architect and implement new ideas to improve Achronix FPGA products
  • Explore and define new vertical technical solutions:
    • Research existing approaches and innovate on them
    • Create prototype implementations
    • Specify requirements for productization
    • Work with engineering to help convert ideas into products
  • Develop and implement proof-of-concept demonstrators and customer-specific point solutions
  • Develop patents
Secondary Job Responsibilities
  • Support sales with customer-oriented case studies:
    • Perform analyses and make proposals to solve customer challenges
    • Prepare and review analyses and presentations
  • Support marketing by developing white papers, online publications and conference submissions
Skills
  • Self-motivated and self-starting team player, collaboration focused
  • Deep expertise on all architectural and implementation aspects of FPGAs
  • FPGA hardware architecture and device modeling
  • Understanding of and proficiency with FPGA user design flows from HLS, RTL to Synthesis, Place-and-Route and STA
  • Proficient in Verilog and SystemVerilog
  • Experience with scripting languages including Tcl
  • Implementation and debug of complex FPGA designs
  • Proven track record on innovations; this may include patents, conference presentations and papers
  • Superb communication skills
  • Strong ability to independently recognize problems and a strong drive toward robust problem resolution
  • Experience with mapping challenging designs to FPGAs and identifying opportunities for PPA improvements
  • Experience with FPGA tools: Synplify, ACE, Vivado/Vitis, Quartus etc.
  • Able to set up and run simulations with Modelsim, VCS or other relevant simulators
  • Knowledge of, and experience with the following domains is a plus:
    • HLS
    • C/C++
    • AI/ML
    • CPU cores
  • Experience with VHDL is a plus
Education and Experience
  • MSEE/MSCE/CS plus 7 years of experience, or equivalent

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