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Vivado Hls Jobs (NOW HIRING)

Principal FPGA Engineer

Fort Wayne, IN

$137K - $167K/yr

AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Using ...

Senior FPGA Design Engineer

Wayne, IN · On-site

$109K - $150K/yr

AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs

Principal FPGA Engineer

Wayne, IN · On-site

$123K - $150K/yr

AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Using ...

Principal FPGA Engineer

Mckinney, TX

$129K - $157K/yr

... AMD Vivado, Altera Quartus Prime Pro or Libero. * Generate FPGA designs for the following ... Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Using ...

Lead Research Engineer

Niskayuna, NY · On-site

$98K - $164K/yr

... Xilinx Vivado) * 2-5 years of solid understanding of digital logic design, including FSMs ... level synthesis (HLS) tools and algorithm-to-hardware workflows, including Vitis HLS and ...

Research Engineer

Niskayuna, NY · On-site

$98K - $164K/yr

... Xilinx Vivado) * 2-5 years of solid understanding of digital logic design, including FSMs ... level synthesis (HLS) tools and algorithm-to-hardware workflows, including Vitis HLS and ...

Lead Engineer - Design

Niskayuna, NY · On-site

$98K - $164K/yr

... Xilinx Vivado) * 2-5 years of solid understanding of digital logic design, including FSMs ... level synthesis (HLS) tools and algorithm-to-hardware workflows, including Vitis HLS and ...

$134K - $195K/yr

Experience with FPGA development tools (e.g., include Quartus, Vivado, etc.) * Experience with VHDL or Verilog or System Verilog or OpenCL or high-level synthesis tools (HLS) * BSEE or related ...

Senior FPGA Engineer

Dayton, OH · On-site

$90 - $120/hr

Mastery of vendor tools such as AMD/Xilinx Vivado, Intel Quartus, or Microchip Libero. * Methodologies: Experience with High-Level Synthesis (HLS), Digital Signal Processing (DSP), and SoC ...

FPGA engineer. Timing. Granada, Spain

Bath, PA · On-site

$119K - $153K/yr

Knowledge of Xilinx FPGA tools and platforms (Vivado, Vitis, HLS, ...). * General understanding of embedded software development, debugging, FPGA logic design and verification. * FPGA logic design ...

Knowledge of Xilinx FPGA development tools and platforms would be valuable (Vivado, Vitis, HLS, ...). FPGA logic design and simulation (VHDL/Verilog) * Experience in embedded software development ...

Sr. FPGA Engineer

El Segundo, CA · On-site

$160K - $225K/yr

Extensive experience with the AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale ... Experience with HLS Synthesis and languages (C/C++/SystemC/Chisel) * Experience with VHDL

FPGA Engineer

El Segundo, CA · On-site

$160K - $225K/yr

Extensive experience with the AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale ... Experience with HLS Synthesis and languages (C/C++/SystemC/Chisel) * Experience with VHDL

Showing results 41-60

Vivado Hls information

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$65.5K

$94.4K

$116K

How much do vivado hls jobs pay per year?

As of Aug 18, 2026, the average yearly pay for vivado hls in the United States is $94,437.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,500.00 and $105,500.00 per year, depending on experience, location, and employer.

What is Vivado HLS?

Vivado HLS (High-Level Synthesis) is a tool developed by Xilinx that allows designers to compile C, C++, or SystemC code into hardware description language (HDL) such as Verilog or VHDL. This process enables faster design cycles for FPGA and ASIC development by allowing engineers to describe hardware behavior using high-level programming languages instead of traditional RTL coding. Vivado HLS is widely used in applications that require rapid prototyping, algorithm acceleration, and design optimization for programmable logic devices.

What skills and qualifications are needed to thrive as a Vivado HLS engineer?

To thrive as a Vivado HLS Engineer, you need a solid background in digital design, C/C++ programming, and FPGA development, often supported by a degree in electrical engineering or related fields. Proficiency with Xilinx Vivado HLS tools, simulation environments, and hardware description languages like VHDL or Verilog is essential. Strong analytical thinking, attention to detail, and effective problem-solving set outstanding engineers apart. These skills ensure efficient translation of algorithms into hardware, optimized FPGA implementations, and successful project outcomes.

What are common challenges engineers face when using Vivado HLS in FPGA development projects?

Engineers working with Vivado HLS often encounter challenges related to optimizing C/C++ code for hardware synthesis, such as balancing resource utilization with performance goals. Understanding how high-level code translates to hardware structures can require a learning curve, especially when debugging timing issues or unexpected synthesis results. Collaboration with RTL engineers and system architects is common, as integration with existing IP and meeting overall system constraints are key aspects of the workflow. Regular review and iteration are typically required to achieve the desired hardware efficiency.

What is Vivado HLS used for?

Vivado HLS (High-Level Synthesis) is used by FPGA design engineers to convert C, C++, and SystemC code into hardware description language (HDL) such as VHDL or Verilog. It streamlines the development process by enabling high-level algorithm modeling and automatic hardware generation, facilitating faster prototyping and implementation of FPGA-based systems.
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Infographic showing various Vivado Hls job openings in the United States as of August 2026, with employment types broken down into 70% Full Time, and 30% Contract. Highlights an 90% In-person, and 10% Remote job distribution, with an average salary of $94,437 per year, or $45.4 per hour.

Senior FPGA Design Engineer with Security Clearance

RTX

Fort Wayne, IN • On-site

$113K - $156K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 24 days ago


RTX rating

8.2

Company rating: 8.2 out of 10

Based on 86 frontline employees who took The Breakroom Quiz

39th of 72 rated aerospace companies


Job description

Date Posted:
2026-06-24
Country:
United States of America Location:
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A Position Role Type:
Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance Security Clearance Type: DoD Clearance: Secret Security Clearance Status: Active and existing security clearance required after day 1 At Raytheon, the foundation of everything we do is rooted in our values and a higher calling - to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today's mission and stay ahead of tomorrow's threat. Our team solves tough, meaningful problems that create a safer, more secure world. The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment. The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions for sensor and effector products. You will partner with experienced, multidisciplinary teams to define requirements, develop architectures, execute detailed design and simulations, and perform integration and verification tasks. You will document your designs within the appropriate configuration management tools and provide comprehensive engineering support throughout the product lifecycle. This position is an onsite role, located in Fort Wayne, IN. What You Will Do * Provide full lifecycle support of production quality FPGA designs for all major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
* Generate FPGA designs for the following applications: gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
* Support translation of system level requirements into FPGA requirements
* Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
* Lead FPGA designs and code in VHDL for reliability and maintainability
* Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
* Define schedules for FPGA tasking and drive execution to the planned budget and schedule.
* Create complete documentation including requirements, verification plan, and user's guides
* Lead individual designs and/or small teams.
* Operate with minimal oversight from manager.
* Support internal and external technical reviews.
* Engage in knowledge transfer activities and mentorship of junior engineers. Qualifications You Must Have * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience.
* Experience to include one or more of the following: * FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
* Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
* Hands on experience with integration and debug of FPGA/ASIC in a lab environment
* Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
* Experience with source code management, design reviews, and code release in a team development environment. Qualifications We Prefer * One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience."
* FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
* Image processing techniques for visual and infrared sensors
* Embedded systems design using ARM, Microblaze, or NIOS processors
* Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
* Constrained random verification in UVM using System Verilog
* Experience with High Level Synthesis (HLS)
* Experience with vector processors and/or GPUs
* Demonstrated ability to lead teams to achieve schedule, budget and technical commitments.
* Experience with project management tools such as Earned Value and/or Agile Execution.
* Proposal development experience. What We Offer Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation. This position offers relocation based on candidate eligibility. Learn More & Apply Now! This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here: https://www.state.gov/m/ds/clearances/c10978.htm Indiana: https://careers.rtx.com/global/en/raytheon-indiana-location #LI-CV1 As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote. The salary range for this role is 86,800 USD - 165,200 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate's work experience, location, education/training, and key skills. Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement. Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company's performance. This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply. RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window. RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans' Readjustment Assistance Act. Privacy Policy and Terms: Click on this link to read the Policy and Terms

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