Proficiency in System Verilog and advanced UVM methodologies is a must. * Good experience in System Verilog assertions. * Own the development of test plans, test environments and test suites used to ...
Proficiency in System Verilog and advanced UVM methodologies is a must. * Good experience in System Verilog assertions. * Own the development of test plans, test environments and test suites used to ...
RTL Design Engineer
Dallas, TX · On-site
Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements ...
RTL Design Engineer
Dallas, TX · On-site
Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements ...
Design Verification Lead Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex ...
Quick apply
Design Verification Lead Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Design Verification Engineer-W EICDV5234
San Jose, CA · On-site
$159.40K - $194.60K/yr
System Verilog,UVM,C+
Design Verification Engineer-W EICDV5234
San Jose, CA · On-site
$159.40K - $194.60K/yr
System Verilog,UVM,C+
Formal Verification Engineer
$144.40K/yr
VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim ...
Formal Verification Engineer
$144.40K/yr
VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Use Verilog to design and System Verilog for block level verification * Assist the Verification team in reviewing and debugging test cases * Run LINT and CDC checks on the RTL code and fix ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Use Verilog to design and System Verilog for block level verification * Assist the Verification team in reviewing and debugging test cases * Run LINT and CDC checks on the RTL code and fix ...
EICDV5235 Design Verification Engineer Onsite
San Jose, CA · On-site
$159.40K - $194.60K/yr
UVM,SOC,Verilog,ASIC
EICDV5235 Design Verification Engineer Onsite
San Jose, CA · On-site
$159.40K - $194.60K/yr
UVM,SOC,Verilog,ASIC
Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL functionality * Run functional simulations and regressions, including gate level and timing annotated ...
Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL functionality * Run functional simulations and regressions, including gate level and timing annotated ...
FPGA Engineer ( Rochester, NY )
$128.30K - $164.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
FPGA Engineer ( Rochester, NY )
$128.30K - $164.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$126.80K - $190.90K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$126.80K - $190.90K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
The ideal candidate will have strong expertise in VHDL or Verilog HDL coding and simulation, along with experience using ModelSim and Xilinx tools. Key Responsibilities: * Implement FPGA-based ...
The ideal candidate will have strong expertise in VHDL or Verilog HDL coding and simulation, along with experience using ModelSim and Xilinx tools. Key Responsibilities: * Implement FPGA-based ...
Systems Engineer (VHDL)
Glen Burnie, MD · On-site
The ideal candidate will have strong expertise in VHDL or Verilog HDL coding and simulation, along with experience using ModelSim and Xilinx tools. Key Responsibilities: * Implement FPGA-based ...
Systems Engineer (VHDL)
Glen Burnie, MD · On-site
The ideal candidate will have strong expertise in VHDL or Verilog HDL coding and simulation, along with experience using ModelSim and Xilinx tools. Key Responsibilities: * Implement FPGA-based ...
FPGA Engineer ( Rochester, NY ) 36890
$129.10K - $165.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
Quick apply
FPGA Engineer ( Rochester, NY ) 36890
$129.10K - $165.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
FPGA Engineer ( Rochester, NY )
$128.30K - $164.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
FPGA Engineer ( Rochester, NY )
$128.30K - $164.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
FPGA Engineer ( Rochester, NY )
Rochester, NY · On-site
$128.30K - $164.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
FPGA Engineer ( Rochester, NY )
Rochester, NY · On-site
$128.30K - $164.80K/yr
Successful candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using System Verilog. Candidate will be required to analyze requirements, create ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Design and implement digital circuits using HDL (Verilog/ System Verilog). * Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis * Optimize designs for ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Design and implement digital circuits using HDL (Verilog/ System Verilog). * Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis * Optimize designs for ...
Verilog information
See salary details
$88K - $98.8K
9% of jobs
$98.8K - $109.6K
2% of jobs
$109.6K - $120.5K
2% of jobs
$120.5K - $131.3K
4% of jobs
$135.1K is the 25th percentile. Wages below this are outliers.
$131.3K - $142.1K
22% of jobs
$142.1K - $152.9K
4% of jobs
The median wage is $163.7K / yr.
$152.9K - $163.7K
6% of jobs
$173.1K is the 75th percentile. Wages above this are outliers.
$163.7K - $174.5K
29% of jobs
$174.5K - $185.4K
9% of jobs
$185.4K - $196.2K
6% of jobs
$196.2K - $207K
6% of jobs
$88K
$156.1K
$207K
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Posted 24 days ago
Job description
Principal Verification Engineer
Job Description:
- Independently architect UVM based verification environments including drivers, monitors, scoreboards, functional checkers, functional coverage.
- Innovative in functional coverage techniques and stress verification with testing all corners of DV - Passing/Failing/Error/breaking scenarios for DUT.
- Own verification at module and/or full chip level.
- Proficiency in System Verilog and advanced UVM methodologies is a must.
- Good experience in System Verilog assertions.
- Own the development of test plans, test environments and test suites used to verify complex Ethernet and Microcontroller SOC products.
- Prior experience as a verification lead is preferred.
- Prior experience of working with and guiding the junior members of the team is required.
Responsibilities:
- Product verification test plan specification
- Drive verification methodologies and practices
- Develop System Verilog verification IP
- Develop chip/block level test environments
- Develop and debug test suites
- Lead and mentor other verification engineers