Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex ...
Quick apply
Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex ...
Quick apply
Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex ...
San Jose, CA · Hybrid
$159K - $195K/yr
Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...
San Jose, CA · Hybrid
$159K - $195K/yr
Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...
Proficiency in System Verilog and advanced UVM methodologies is a must. * Good experience in System Verilog assertions. * Own the development of test plans, test environments and test suites used to ...
Proficiency in System Verilog and advanced UVM methodologies is a must. * Good experience in System Verilog assertions. * Own the development of test plans, test environments and test suites used to ...
Verification of Verilog modules with automated test benches using ModelSim / QuestaSim * Test and commissioning of the functions on the hardware * Bachelor's or master's degree in electrical ...
Verification of Verilog modules with automated test benches using ModelSim / QuestaSim * Test and commissioning of the functions on the hardware * Bachelor's or master's degree in electrical ...
Austin, TX · On-site
$134K - $164K/yr
Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases. * Defining and writing System Verilog Assertion (SVA) cover properties to match the verification ...
Austin, TX · On-site
$134K - $164K/yr
Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases. * Defining and writing System Verilog Assertion (SVA) cover properties to match the verification ...
Dallas, TX · On-site
Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements ...
Dallas, TX · On-site
Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements ...
$134K - $164K/yr
Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases. * Defining and writing System Verilog Assertion (SVA) cover properties to match the verification ...
$134K - $164K/yr
Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases. * Defining and writing System Verilog Assertion (SVA) cover properties to match the verification ...
San Jose, CA · On-site
$159K - $194K/yr
System Verilog,UVM,C+
San Jose, CA · On-site
$159K - $194K/yr
System Verilog,UVM,C+
$118K - $162K/yr
The primary responsibilities will focus on Verilog FPGA design verification, and the System Verilog UVM framework verification. Essential Functions: * Analysis of the requirements, architecture ...
$118K - $162K/yr
The primary responsibilities will focus on Verilog FPGA design verification, and the System Verilog UVM framework verification. Essential Functions: * Analysis of the requirements, architecture ...
Santa Clara, CA · On-site
$159K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Santa Clara, CA · On-site
$159K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Cincinnati, OH · On-site
Bachelor''s Degree, Verilog, "C" Programming for embedded systems, Algorithm Development, data structures, Logic Analyzers, oscilloscopes, JTAG/ICE debuggers, protocol analyzers, firmware development ...
Cincinnati, OH · On-site
Bachelor''s Degree, Verilog, "C" Programming for embedded systems, Algorithm Development, data structures, Logic Analyzers, oscilloscopes, JTAG/ICE debuggers, protocol analyzers, firmware development ...
Cincinnati, OH · On-site
$106K - $197K/yr
Please apply ONLY if you have extensive FPGA and Verilog experience United States Citizenship is required due to government contract requirements We can ONLY consider your application if you have: 1: ...
Cincinnati, OH · On-site
$106K - $197K/yr
Please apply ONLY if you have extensive FPGA and Verilog experience United States Citizenship is required due to government contract requirements We can ONLY consider your application if you have: 1: ...
San Jose, CA · On-site
$159K - $194K/yr
UVM,SOC,Verilog,ASIC
San Jose, CA · On-site
$159K - $194K/yr
UVM,SOC,Verilog,ASIC
Santa Clara, CA · On-site
$159K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Santa Clara, CA · On-site
$159K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Santa Clara, CA · On-site
$159K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Santa Clara, CA · On-site
$159K/yr
Aid silicon debug in related part of the design • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered • Develop checkers or Verilog/System ...
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
San Diego, CA · On-site
$144K/yr
Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog, checkers, and other design verification techniques * Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing ...
San Diego, CA · On-site
$144K/yr
Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog, checkers, and other design verification techniques * Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing ...
VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim ...
VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim ...
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
San Diego, CA · On-site
$145K - $178K/yr
We are seeking a skilled Design Verification Engineer with strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in ...
San Diego, CA · On-site
$145K - $178K/yr
We are seeking a skilled Design Verification Engineer with strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in ...
$88K - $98.8K
9% of jobs
$98.8K - $109.6K
2% of jobs
$109.6K - $120.5K
2% of jobs
$120.5K - $131.3K
4% of jobs
$135.1K is the 25th percentile. Wages below this are outliers.
$131.3K - $142.1K
22% of jobs
$142.1K - $152.9K
4% of jobs
The median wage is $163.7K / yr.
$152.9K - $163.7K
6% of jobs
$173.1K is the 75th percentile. Wages above this are outliers.
$163.7K - $174.5K
29% of jobs
$174.5K - $185.4K
9% of jobs
$185.4K - $196.2K
6% of jobs
$196.2K - $207K
6% of jobs
$88K
$156.1K
$207K
A typical day in a Verilog role involves writing and modifying Verilog code to describe digital circuits, running simulations to verify design functionality, and debugging hardware issues in collaboration with other engineers. You might also interact with hardware engineers, verification teams, and project managers to ensure project milestones are met. Regular review meetings and design documentation are integral parts of the workflow, and you’ll often switch between independent tasks and team-based problem-solving. The work environment is usually dynamic and deadline-driven, offering opportunities to learn about cutting-edge hardware technologies.
To excel in a Verilog role, you need a deep understanding of digital logic design, hardware description languages (especially Verilog), and often a degree in electrical or computer engineering. Experience with simulation tools like ModelSim, EDA tools such as Synopsys or Cadence, and potentially industry certifications like FPGA or ASIC design are highly valued. Strong analytical thinking, problem-solving skills, and effective teamwork are important soft skills in this field. These competencies are essential for creating reliable, efficient hardware designs and collaborating within multidisciplinary engineering teams.
A Verilog job typically involves designing, simulating, and verifying digital circuits using Verilog, a hardware description language (HDL). Engineers in this role work on FPGA and ASIC development for applications such as processors, communication systems, and embedded hardware. Responsibilities often include writing Verilog code, performing design synthesis, and debugging hardware using simulation tools. Verilog engineers are commonly employed in semiconductor, aerospace, and consumer electronics industries.

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