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Pcie Verification Engineer Jobs (NOW HIRING)

Insilico

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ... PCIE verification background 2. 400G MAC verification background Qualifications Additional ...

Insilico

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

... PCIE verification background 2. 400G MAC verification background Additional Information All your information will be kept confidential according to EEO guidelines.

ARM

Principal PCIe Subsystem Verification Engineer

Austin, TX · On-site

$249K - $338K/yr

... Engineering (or similar field) over 5+ years of experience working in verification of sophisticated PCIe or CXL subsystems or SoCs, you will need: * Solid understanding of digital hardware design and ...

R3 Tek

Verification Engineer

San Francisco, CA · On-site

$160K/yr

Verification Engineer Location: San Francisco Bay Area, CA Employment Type: Contract Required ... in PCIe Gen3, Gen4 protocols is necessary 2) Expertise in SPI, JTAG, and Transceiver PHY is ...

ARM

Staff Verification Engineer

Austin, TX · Hybrid

$191K - $258K/yr

Arm's Solutions Engineering team is looking for experienced PCIe and CXL experts in verifying and ... New team members will join hands with other Architects, RTL design and verification engineers ...

R3 Tek

Verification Engineer

San Francisco, CA

$160K/yr

Verification Engineer Location: San Francisco Bay Area, CA Employment Type: Contract /Contract to ... in PCIe Gen3, Gen4 protocols is necessary 2) Expertise in SPI, JTAG , and Transceiver PHY is ...

ARM

Staff Verification Engineer

Austin, TX · On-site

$191K - $258K/yr

Arm's Solutions Engineering team is looking for experienced PCIe and CXL experts in verifying and ... New team members will join hands with other Architects, RTL design and verification engineers ...

7Rays Semiconductors

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

We are seeking a highly motivated Design Verification Engineer to join our Interface IP DV team ... PCIe * Ethernet * CPU subsystems (ARC/ARM) * Low-power peripherals * Sensors * Understand vendor IP ...

Embtel Inc

Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Staff Verification Engineer Office Located in Campbell, CA ( 100 % remote considered) Duration ... Ethernet, PCIe, DDR is mandatory. Expertise in formal verification flows and techniques. Strong ...

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All JobsPcie Verification Engineer Jobs

Pcie Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do pcie verification engineer jobs pay per year?

As of Jul 25, 2026, the average yearly pay for pcie verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a PCIe Verification Engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe Verification Engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe Verification Engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

More about Pcie Verification Engineer jobs
What cities are hiring for Pcie Verification Engineer jobs? Cities with the most Pcie Verification Engineer job openings:
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Pcie Verification Engineer jobs near you
Infographic showing various Pcie Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 50% Full Time, and 50% Contract. Highlights an 100% In-person job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Principal Engineer, PCIe Verification (AI2441)

SiMa Technologies

San Jose, CA

$220K - $296K/yr

Full-time

Posted 25 days ago

Job description

Job Title: Principal Engineer, PCIe Verification        
     
Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) 
     
Job ID: AI2441   
     
Description:   
    
The Design Verification (DV) engineer at SiMa is involved in the functional verification of PCIe controller and PCIe-phy at block, sub-system and MLSoC level. Will also be involved in PCIe bring-up and debug on emulator. Generate required PCIe controller and phy initialization (register programming code sequence) for PCIe bring up in Simulation, emulation and on silicon. Work on UCIe interface verification on next generation projects. 
 
Job Description: 
 
As the PCIe Design Verification Engineer, you will  
  • Participate in PCIe architecture, micro-architecture, feature discussions and reviews. 
  • Define and develop PCIe test bench components using UVM & System Verilog. 
  • Bring up and testing of PCIe in block and full-chip test environment. 
  • Develop and execute a test plan. 
  • Verification execution of PCIe EP/RC functionality and performance measurements. 
  • Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure. 
  • Manage debug of test and regression failures, as well emulation failures.  
  • Work closely with the Architecture, MLSoC Hardware and MLA Software teams. 
  • Work with emulation and MLSoC Software team to bring up and debug PCIe. 
  • Work in the lab on PCie interface silicon debug with software and systems team as and when needed. 
 
Required Background: 
  • BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring-up/debug. 
  • Very good current working experience of UVM and System Verilog based verification methodology is a must. 
  • Working experience on PCIe protocols Gen4/5. 
  • Working experience on PCIe bring-up and debug on Silicon is a plus. 
  • Past working experience on UCIe protocols is a plus. 
  • Proficiency in C/C++/Python programming is a plus.
  • Good debug and problem solving skill.
  
Personal attributes:  
     
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.  
    
The annual salary for this position ranges from $220,000 - $296,400. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.   
 
In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.
       
     
EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.