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Pcie Verification Engineer Jobs (NOW HIRING)

Insilico

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

... PCIE verification background 2. 400G MAC verification background Additional Information All your information will be kept confidential according to EEO guidelines.

Insilico

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ... PCIE verification background 2. 400G MAC verification background Qualifications Additional ...

Altera

Design Verification Engineer

San Jose, CA

$159K - $194K/yr

About the Role We are seeking a highly experienced Design Verification Engineer to join Altera ... Integrate and validate third-party PCIe VIP models and co-simulate with firmware and software ...

R3 Tek

Verification Engineer

San Francisco, CA

$160K/yr

Verification Engineer Location: San Francisco Bay Area, CA Employment Type: Contract Required ... in PCIe Gen3, Gen4 protocols is necessary 2) Expertise in SPI, JTAG, and Transceiver PHY is ...

R3 Tek

Verification Engineer

San Francisco, CA

$160K/yr

Verification Engineer Location: San Francisco Bay Area, CA Employment Type: Contract /Contract to ... in PCIe Gen3, Gen4 protocols is necessary 2) Expertise in SPI, JTAG , and Transceiver PHY is ...

Embtel Inc

Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Staff Verification Engineer Office Located in Campbell, CA ( 100 % remote considered) Duration ... Ethernet, PCIe, DDR is mandatory. Expertise in formal verification flows and techniques. Strong ...

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114K - $157K/yr

Job Title- Senior Verification Engineer Project Location - On-site 5 days Lake Ronkonkoma NY (Long ... Validate high-speed interfaces and protocols including PCIe, 1G/10G Ethernet, and TSN. * Support DO ...

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All JobsPcie Verification Engineer Jobs

Pcie Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do pcie verification engineer jobs pay per year?

As of Jun 14, 2026, the average yearly pay for pcie verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a PCIe Verification Engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe Verification Engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe Verification Engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

More about Pcie Verification Engineer jobs
What cities are hiring for Pcie Verification Engineer jobs? Cities with the most Pcie Verification Engineer job openings:
What states have the most Pcie Verification Engineer jobs? States with the most job openings for Pcie Verification Engineer jobs include:
What job categories do people searching Pcie Verification Engineer jobs look for? The top searched job categories for Pcie Verification Engineer jobs are:
Pcie Verification Engineer jobs near you
Infographic showing various Pcie Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 1% As Needed, 85% Full Time, 11% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
PCIe Verification Engineer

PCIe Verification Engineer

Advanced Micro Devices, Inc

San Jose, CA • On-site

$175K/yr

Full-time

Posted 9 days ago

Advanced Micro Devices rating

8.4

Company rating: 8.4 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

23rd of 139 rated electronics manufacturers

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.
THE PERSON:
You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
  • Build the directed and random verification tests
  • Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

PREFERRED EXPERIENCE:
  • Proficient in IP level ASIC verification
  • Expert in Verilog, System Verilog, Object Oriented programming
  • Developing UVM based verification frameworks and testbenches,
  • Scripting and automation of verification processes and flows
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Good Computer Architecture, systems knowledge
  • Comfortable in python / perl and editing / maintaining scripts
  • Exposure to leadership or mentorship is an asset
  • Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
  • Experience with PCIe, CXL, NVMe or ethernet protocols
  • Strong communication skills and the ability to work independently as well as in a cross-site team environment

ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: San Jose, CA, OR San Diego, CA OR Austin, TX OR Longmont, CO
#LI-TB2
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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