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Pcie Verification Engineer Jobs in Bothell, WA (NOW HIRING)

K2 Space

Senior FPGA Engineer

Seattle, WA · On-site

$120K - $225K/yr

As a part of the team, you will be responsible for the development and verification of FPGA ... Experience implementing high-speed SERDES interfaces such as Ethernet, PCIe, and JESD204C.

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA

$170K - $250K/yr

Accelerate overall verification throughput by helping DV team run targeted and highvalue tests in ... Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit ...

Amazon

Sr. FPGA Engineer, Amazon Leo

Redmond, WA · On-site

$145K - $187K/yr

This role will contribute to the design, development, and verification of FPGA-based prototypes for ... speed interfaces (PCIe, Ethernet, SERDES, etc.) PREFERRED QUALIFICATIONS - Experience with ...

Programmers.io

EE Test Engineer

Redmond, WA · On-site

... PHY, PCIe, USB SS, and UFS), electrical performance of subsystems such Display, Camera/Vision ... System Verification for consumer electronics - experience with mobile technology (smartphone ...

K2 Space

Senior FPGA Engineer

Seattle, WA · On-site

$120K - $225K/yr

As a part of the team, you will be responsible for the development and verification of FPGA ... Experience implementing high-speed SERDES interfaces such as Ethernet, PCIe, and JESD204C.

K2 Space

Senior FPGA Engineer

Seattle, WA

$120K - $225K/yr

As a part of the team, you will be responsible for the development and verification of FPGA ... Experience implementing high-speed SERDES interfaces such as Ethernet, PCIe, and JESD204C.

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Pcie Verification Engineer information

See Bothell, WA salary details

$89.4K

$159.4K

$227.5K

How much do pcie verification engineer jobs pay per year?

As of Aug 8, 2026, the average yearly pay for pcie verification engineer in Bothell, WA is $159,432.00, according to ZipRecruiter salary data. Most workers in this role earn between $152,000.00 and $152,000.00 per year, depending on experience, location, and employer.

What does a PCIe verification engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe verification engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe verification engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

What job categories do people searching Pcie Verification Engineer jobs in Bothell, WA look for? The top searched job categories for Pcie Verification Engineer jobs in Bothell, WA are:
What cities near Bothell, WA are hiring for Pcie Verification Engineer jobs? Cities near Bothell, WA with the most Pcie Verification Engineer job openings:
Pcie Verification Engineer jobs near you

Senior PCIe Bridge Design Verification Engineer

Microsoft

Redmond, WA • On-site

$117K - $160K/yr

Full-time

This job post has expired 1 day ago. Applications are no longer accepted.

Microsoft rating

8.5

Company rating: 8.5 out of 10

Based on 132 frontline employees who took The Breakroom Quiz

78th of 242 rated software companies

Job description

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior PCIe Bridge Design Verification Engineer to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for Senior PCIe Bridge Design Verification Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior PCIe Bridge Design Verification Engineer to join the team.
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
  • Own or lead verification of complex Peripheral Component Interconnect Express (PCIe) Bridge IP flows
  • Learn about the design and interact with partner teams to define verification strategies and test plans
  • Develop UVM-based verification environments and run and debug simulations to drive quality
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  • Innovate to improve verification efficiency through methodologies or tools
  • Apply industry leading generative AI solutions to verification work
  • Share expertise and support the growth and development of others through coaching, mentorship, and collaboration.
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Qualifications
Required Qualifications:
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Other Requirements:
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:
  • 5+ years of pre-silicon subsystem or IP verification experience.
  • 3+ years of PCIe experience.
  • 7+ years of related technical engineering experience
    • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience
    • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience.
    • OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
  • Demonstrated experience in verifying designs that utilize PCIe, Coherent Hub Interface (CHI) and Advanced eXtensible Interface (AXI) protocols and/or protocol bridges
  • Experience driving IP verification for a full product cycle from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff
  • Demonstrated hands-on technical leadership such as creating bottom's up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
  • Aptitude for writing scripts/software with industry standard languages like Python
  • Experience applying generative AI to day-to-day tasks

#SCHIE #CSME
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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