ZipRecruiter

Log In

1

Pcie Verification Engineer Jobs (NOW HIRING)

idexcel

SoC Verification Engineer

San Jose, CA

$159K/yr

San Jose, CA Duration: 6-12 Months Candidates must have either in USB or PCIe or Ethernet. Job Details: Candidate must have 7+ years of experience in Verification . Must have experience in ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)

Eridu AI

Verification Engineer

Saratoga, CA · On-site

$195K - $265K/yr

The company is in execution mode and has a world-class engineering team with decades of experience ... Prior experience with Ethernet and PCIe Protocols, Serial and Parallel VIP verification modes and ...

next page

Showing results 1-20

All JobsPcie Verification Engineer Jobs

Pcie Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do pcie verification engineer jobs pay per year?

As of Jun 15, 2026, the average yearly pay for pcie verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a PCIe Verification Engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe Verification Engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe Verification Engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

More about Pcie Verification Engineer jobs
What cities are hiring for Pcie Verification Engineer jobs? Cities with the most Pcie Verification Engineer job openings:
What states have the most Pcie Verification Engineer jobs? States with the most job openings for Pcie Verification Engineer jobs include:
What job categories do people searching Pcie Verification Engineer jobs look for? The top searched job categories for Pcie Verification Engineer jobs are:
Pcie Verification Engineer jobs near you
Infographic showing various Pcie Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 1% As Needed, 85% Full Time, 11% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Senior Staff Design Verification Engineer - PCIE/CXL Sub-System

Senior Staff Design Verification Engineer - PCIE/CXL Sub-System

Marvell Technology, Inc.

Irvine, CA • On-site

$146K - $178K/yr

Full-time

Life, Retirement

Posted 25 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Center of Excellence (COE), part of the Custom Compute and Storage (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems - spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle - sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.
What You Can Expect
  • Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems, from test planning through coverage closure and signoff
  • Define and execute comprehensive verification plans based on protocol specifications and micro-architecture requirements
  • Architect and develop scalable UVM/System Verilog testbenches for PCIe/CXL controllers and fabric-level subsystems
  • Integrate and configure PCIe/CXL VIP for subsystem and system-level verification environments
  • Validate CXL.io, CXL.cache, and CXL.mem protocols, including coherency and memory semantics across complex flows
  • Develop constrained-random and directed test suites to achieve high functional coverage across corner and stress scenarios
  • Debug complex failures such as protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers
  • Implement System Verilog Assertions (SVA) for protocol compliance, improving early bug detection and debug efficiency
  • Drive functional, code, and assertion coverage closure, identifying gaps and developing targeted tests to meet signoff goals
  • Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads
  • Develop automation (Python/Shell) for regression management, log triage, and coverage reporting, improving productivity
  • Collaborate with design, architecture, firmware and validation teams, influencing design-for-verification and mentoring junior engineers

What We're Looking For
Required Qualifications:
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
  • 5-10 years of experience in ASIC/SoC verification
  • Strong knowledge of PCIE and CXL protocols and architecture
  • Expertise in System Verilog and UVM methodology
  • Experience with debugging complex verification issues
  • Familiarity with industry-standard tools (e.g., simulation, waveform debugging, coverage tools)
  • Solid understanding of digital design fundamentals

Additional Preferred Qualifications:
  • Experience with assertion-based verification (SVA)
  • Exposure to performance modeling and traffic generation
  • Exposure to emulation platforms (e.g., Palladium, Veloce) a plus
  • Scripting skills (Python/Perl/Shell)
  • Experience with low-power verification (UPF)
  • Develop and execute verification plans for high-speed memory interfaces (PCIE 6/7, CXL 3.2/4.0)
  • Build and enhance UVM/System Verilog-based verification environments
  • Develop test benches, sequences, and checkers for functional and performance validation
  • Perform protocol-level verification for PCIE controllers and PHY interfaces
  • Analyze and debug simulation failures, identify root causes, and drive resolution
  • Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance
  • Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage
  • Support emulation/FPGA validation and post-silicon bring-up (nice to have)
  • Review design specifications and provide feedback for testability and robustness

Expected Base Pay Range (USD)
135,900 - 201,130, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
#LI-JT2

Apply