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Pcie Verification Engineer Jobs (NOW HIRING)

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site

... ASIC Design Engineer to lead the design and integration of PCIe controllers into our next ... Collaborate with IP vendors, architecture, verification, physical design, and software teams to ...

idexcel

SoC Verification Engineer

San Jose, CA

$159K/yr

San Jose, CA Duration: 6-12 Months Candidates must have either in USB or PCIe or Ethernet. Job Details: Candidate must have 7+ years of experience in Verification . Must have experience in ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)

Eridu AI

Verification Engineer

Saratoga, CA · On-site

$195K - $265K/yr

The company is in execution mode and has a world-class engineering team with decades of experience ... Prior experience with Ethernet and PCIe Protocols, Serial and Parallel VIP verification modes and ...

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Pcie Verification Engineer information

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$80K

$142.6K

$203.5K

How much do pcie verification engineer jobs pay per year?

As of Jul 5, 2026, the average yearly pay for pcie verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a PCIe Verification Engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe Verification Engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe Verification Engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

More about Pcie Verification Engineer jobs
What cities are hiring for Pcie Verification Engineer jobs? Cities with the most Pcie Verification Engineer job openings:
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Pcie Verification Engineer jobs near you
Infographic showing various Pcie Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 8% Full Time, and 92% Part Time. Highlights an 92% Physical, 5% Hybrid, and 3% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
PCIe ASIC Design Engineer

PCIe ASIC Design Engineer

Cornelis Networks

Austin, TX • On-site

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 20 days ago

Job description

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.
Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.
We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.
Cornelis Networks is hiring a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6), integration into high performance ASICs, emulation and post silicon bring-up.
Key Responsibilities:
  • Own end-to-end integration of PCIe IP into complex ASIC designs.
  • Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
  • Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
  • Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
  • Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
  • Debug functional and performance issues at RTL, gate-level, and silicon.
  • Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
  • Provide mentorship to junior engineers and help define PCIe subsystem development best practices.
  • Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms

Minimum Qualifications:
  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
  • Proven experience in silicon bring-up and debug of high-speed interfaces.
  • Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
  • Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
  • Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
  • Strong scripting (Python, Perl, TCL) and debugging skills.
  • Strong verbal and written communication skills.

Preferred Qualifications:
  • Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
  • Exposure to CXL, CCIX, or other cache-coherent interconnects.
  • Background in data center or AI/ML accelerator architectures.
  • Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation.

Location: This is a remote position for employees residing within the United States.
We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.
At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.
In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.
Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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