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Pcie Verification Engineer Jobs (NOW HIRING)

Lumilens

Verification Engineer

San Jose, CA · On-site

$159K/yr

  • Medical

  • Dental

  • Vision

You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... UCIe, PCIe/CXL, Ethernet, or UALink VIP / compliance experience . * Mixed-signal verification ...

Eridu AI

Verification Engineer

Saratoga, CA · On-site

$195K - $265K/yr

The company is in execution mode and has a world-class engineering team with decades of experience ... Prior experience with Ethernet and PCIe Protocols, Serial and Parallel VIP verification modes and ...

Ericsson Inc.

ASIC Verification Engineer

Austin, TX · On-site

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

Design Verification Engineer - ASIC IP Company: Ericsson Silicon Location: Austin, Texas This is an ... SerDes, PCIe, ARM subsystems, DSPs/accelerators, or Ethernet Proficiency in scripting languages ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)

Ericsson

ASIC Verification Engineer

Austin, TX · On-site

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

Design Verification Engineer - ASIC IP Company: Ericsson Silicon Location: Austin, Texas This is an ... SerDes, PCIe, ARM subsystems, DSPs/accelerators, or Ethernet Proficiency in scripting languages ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

Nvidia

System Verification Engineer

Santa Clara, CA · On-site

$159K/yr

Bring-up and verify High Speed protocols like PCIe/CXL/NVLINK/IB/Ethernet etc .... Low speed ... S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe ...

Glow Networks

SOC Design Verification Engineer

Dallas, TX · On-site

$127K - $156K/yr

SOC Design Verification Engineer Location: Redmond, WA (Onsite) Duration: 10 Months Minimum ... like PCIe, DDR, Ethernet. • Experience working across and building relationships with cross ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

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Showing results 41-60

All JobsPcie Verification Engineer Jobs

Pcie Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do pcie verification engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for pcie verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a PCIe verification engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe verification engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe verification engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

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Pcie Verification Engineer jobs near you
Infographic showing various Pcie Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Verification Engineer

Lumilens

San Jose, CA • On-site

$159K/yr

Full-time

Medical, Dental, Vision

Re-posted 9 days ago

Job description

About Lumilens
At Lumilens we are building the critical photonics infrastructure that powers tomorrow's AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.
We're a well-funded startup backed by Mayfield and led by veterans who've built and scaled some of the most transformative technologies in the industry.
This isn't incremental innovation, it's a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we're moving faster. You'll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We're just getting started.
About the Role
You verify the blocks and subsystems of a first-of-its-kind chiplet - building UVM testbenches, writing tests, and driving coverage to closure. Guided by the verification plan and methodology, you take assigned blocks from testbench bring-up through coverage signoff, and help debug across simulation and emulation. It's a hands-on role with room to grow your scope as the team and the chip mature.
What You'll Do
  • Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
  • Write directed and constrained-random tests; develop functional coverage and drive it to closure.
  • Verify the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.
  • Integrate and use VIP (e.g., UCIe) and run compliance, link-training, loopback, and lane-repair scenarios.
  • Run regressions, triage failures, and help maintain the CI/regression flow.
  • Register (UVM RAL) verification, firmware co-simulation, and boot flows on the MCU subsystem.
  • Mixed-signal co-simulation - verifying digital blocks against behavioral / real-number models of analog/mixed-signal blocks.
  • Support hardware-assisted verification - bring up and run tests on emulation / FPGA prototyping.
  • Participate in gate-level and low-power (UPF) verification during signoff.
  • Collaborate with the design, architecture, modelling, and DFT teams as your blocks move through the flow.

Required
  • BS or MS in Electrical/Computer Engineering (or equivalent experience).
  • 3+ years of ASIC/SoC functional verification.
  • Solid UVM/SystemVerilog; constrained-random and coverage-driven verification.
  • Testbench development and coverage closure - building block/subsystem testbenches and driving functional + code coverage to closure.
  • Strong debug skills across simulation; scripting in Python, Perl, or TCL.
  • Familiarity with regression/CI flows and failure triage.

Preferred
  • High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification.
  • UCIe, PCIe/CXL, Ethernet, or UALink VIP / compliance experience.
  • Mixed-signal verification (Verilog-AMS or SV real-number models).
  • Hardware-assisted verification - emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
  • Low-power/UPF and gate-level simulation; performance-verification methodology.
  • Exposure to NICs, Ethernet/IB switches, or cache-coherent fabrics (multi-core / coherent fabric).
  • Formal verification for control/interlock logic; portable stimulus.

What We Offer
  • Competitive salary commensurate with experience
  • Comprehensive benefits package including health, dental, and vision
  • Professional development opportunities and certification support
  • Access to cutting-edge technology and cloud platforms
  • Collaborative work environment with cross-functional teams

Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.

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