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Pcie Verification Engineer Jobs (NOW HIRING)

DESIGN VERIFICATION ENGINEER City: Sunnyvale State/Province: California Posting Start Date: 5/27/26 ... Looking for coherency knowledge (if possible) and complex topics in PCIe (like ordering etc)

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member ... such as PCIe or USB, parallel protocol such as DDRBasic knowledge of formal verification ...

Bring-up and verify High Speed protocols like PCIe/CXL/NVLINK/IB/Ethernet etc .... Low speed ... S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe ...

Design Verification Engineer

Los Angeles, CA · On-site

$146K - $178K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member ... such as PCIe or USB, parallel protocol such as DDRBasic knowledge of formal verification ...

SOC Design Verification Engineer

Dallas, TX · On-site

$127K - $156K/yr

SOC Design Verification Engineer Location: Redmond, WA (Onsite) Duration: 10 Months Minimum ... like PCIe, DDR, Ethernet. • Experience working across and building relationships with cross ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

This role is for a DV engineer who will enable us to produce fully functional first silicon for IP ... such as PCIe or USB, parallel protocol such as DDRBasic knowledge of formal verification ...

Design Verification Engineer

Los Angeles, CA · On-site

$146K - $178K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... PCIe or USB, parallel protocol such as DDR is a plus but not requiredKnowledge of formal ...

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM ...

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Pcie Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do pcie verification engineer jobs pay per year?

As of Jun 15, 2026, the average yearly pay for pcie verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a PCIe Verification Engineer do?

A PCIe Verification Engineer is responsible for ensuring that PCI Express (PCIe) hardware and systems function correctly and comply with industry standards. They develop and execute test plans, create verification environments, and use simulation tools to find and resolve design issues. Their work is crucial for validating the performance, reliability, and interoperability of PCIe-based products such as computer motherboards, servers, and storage devices. This role typically requires a strong background in digital design, hardware description languages (HDL), and PCIe protocol knowledge.

What are the key skills and qualifications needed to thrive as a PCIe Verification Engineer, and why are they important?

To thrive as a PCIe Verification Engineer, you need a strong background in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Proficiency with hardware description languages (HDL) like Verilog/SystemVerilog, UVM methodology, simulation tools, and familiarity with PCIe protocol analyzers is essential. Analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex issues and collaborating with cross-functional teams. These competencies ensure reliable product validation, compliance with industry standards, and efficient project delivery in high-speed interface development.

What are some common challenges faced by PCIe Verification Engineers during the verification process?

PCIe Verification Engineers often encounter challenges such as handling the complexity of the PCIe protocol, ensuring compliance with evolving standards, and debugging intricate issues that arise during simulation. The verification process may involve working with large-scale testbenches, managing interoperability testing with different vendors’ devices, and identifying corner-case bugs. Collaboration with both design and software teams is crucial to resolve issues effectively and ensure robust system-level functionality.

What is the difference between Pcie Verification Engineer vs Hardware Verification Engineer?

AspectPcie Verification EngineerHardware Verification Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of PCIe protocolsBachelor's in Electrical Engineering or Computer Engineering; knowledge of hardware protocols
Work EnvironmentDesign teams, FPGA/ASIC verification labsHardware design and testing labs, FPGA/ASIC environments
Industry UsageSemiconductor, computer hardware, embedded systemsSemiconductor, consumer electronics, aerospace
Common Search/ComparisonYesYes

The Pcie Verification Engineer focuses specifically on verifying PCIe interfaces and protocols within hardware designs, while the Hardware Verification Engineer has a broader scope, testing various hardware components and systems. Both roles require similar technical skills and often work in overlapping environments, but their focus areas differ significantly.

More about Pcie Verification Engineer jobs
What cities are hiring for Pcie Verification Engineer jobs? Cities with the most Pcie Verification Engineer job openings:
What states have the most Pcie Verification Engineer jobs? States with the most job openings for Pcie Verification Engineer jobs include:
What job categories do people searching Pcie Verification Engineer jobs look for? The top searched job categories for Pcie Verification Engineer jobs are:
Infographic showing various Pcie Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 1% As Needed, 85% Full Time, 11% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Lead Software Engineer

Lead Software Engineer

Cadence Design Systems Inc.

San Jose, CA • On-site

$114K - $213K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 12 days ago


Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is the industry leader of Verification IP (VIP) with products supporting several communication protocols and memory interfaces. Cadence VIP fits into nearly every verification environment with support for all major simulators and verification languages. Our VIP delivers the advanced features that you need to maximize your productivity and keep projects moving forward.

Our VIP PCIe R&D team is looking for a self-motivated, hands-on, and creative Lead Software Engineer who can be part of PCIe verification IP team and development efforts of the most complex industry leading software solutions for hardware/SOC memory and protocol verification. This industry-leading and proven technology is critically important for state-of-the-art products that are existing or under development

Responsibilities:

Candidate will be responsible for software development and validation of PCIe Verification IP. As a Lead Software Engineer, candidate is expected to participate in development efforts of the PCIe product to meet customer use model, solution requirements, protocol specification and execute necessary SW development practices to create reusable robust software solution to enable verification of these interface protocols. Candidate should be able to work with multi-site and diverse team. You need to effectively collaborate multi location development team to contribute in PCIe verification IP development, milestones technical roadmap and people training for success.

The candidate is also expected work with technical support lead and key customers to resolve implementation or usage issues as Cadence VIP products are used within various verification environments and timing critical to our customer's successes.

Position Requirements

Requirements:

  • BS with a minimum of 4 years of experience OR MS with a minimum of 2 years of experience OR new PhD Graduate
  • Extensive experience in modeling in C/C++ and background in object-oriented, algorithms, and data structures.
  • In-depth understanding of space/time complexity and advanced debugging techniques for proficiency in troubleshooting software issues and debugging a large codebase.
  • Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.
  • Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment.

Strong Plus:

  • Working knowledge of PCI Express (PCIe) protocol or one or more protocols USB, NVME, SATA, Display Port, etc.
  • Knowledge of Verilog/SystemVerilog languages and OVM/UVM verification methodologies.
  • Experience with digital logic design or IP/SoC level Verification flow.
  • Customer orientation and knowledge of the EDA tool flow.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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