Are you an experienced Design Verification Engineer with strong SystemVerilog (SV) & UVM expertise? We're looking for highly skilled professionals to join an exciting hardware verification project.
📍 Locations:
• Sunnyvale, CA
• Austin, TX
💼 Experience Required: 9+ Years
🔹 Key Skills:
✅ Strong hands-on experience with SystemVerilog (SV) & UVM (Must Have)
✅ IP, Sub-system & SoC Level Verification
✅ Verification Testbench Development
✅ Functional Test Development
✅ Verilog & C/C++ Based Verification
✅ Functional & Code Coverage Closure
✅ Debugging & Root Cause Analysis
✅ Design Verification Infrastructure Development
✅ End-to-End Verification Cycle Execution
✅ Experience with OVM methodologies is a plus
✅ Strong collaboration with Design, Emulation & Silicon Validation teams
🎓 Qualifications:
✔ Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science
💡 If you're passionate about building high-quality silicon and have deep expertise in SV/UVM-based verification, we'd love to hear from you!
📩 Apply Now: vijay@aiaxiss.com