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Asic Verification Engineer Remote Jobs in Austin, TX

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on ...

Meta

ASIC Engineer, Design Verification

Austin, TX

$178K/yr

ASIC Engineer, Design Verification Responsibilities: * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification * Develop ...

Meta

ASIC Engineer, Power

Austin, TX · On-site +1

$146K/yr

As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Retym

Senior MXS Verification engineer

Austin, TX · On-site +1

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Sr Mixed signal verification engineer.

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Asic Verification Engineer Remote information

See Austin, TX salary details

$87.2K

$154.7K

$205.2K

How much do asic verification engineer remote jobs pay per year?

As of Aug 10, 2026, the average yearly pay for asic verification engineer remote in Austin, TX is $154,705.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,800.00 and $174,000.00 per year, depending on experience, location, and employer.

What does an ASIC Verification Engineer do?

An ASIC Verification Engineer is responsible for ensuring that an Application-Specific Integrated Circuit (ASIC) design functions as intended before it is manufactured. They develop and implement test plans, create verification environments using hardware description and verification languages like SystemVerilog or UVM, and run simulations to detect design flaws. Working remotely, these engineers collaborate with design teams using digital tools and communication platforms to review specifications, debug issues, and validate functionality. Their work is critical to reducing errors, saving costs, and ensuring high-quality chip production.

What are the main challenges of working remotely as an ASIC Verification Engineer, and how can they be addressed?

One of the main challenges of working remotely as an ASIC Verification Engineer is effective collaboration with design and verification teams, especially when debugging complex issues that benefit from real-time, face-to-face communication. Additionally, accessing hardware labs or simulation environments may require coordination with on-site colleagues. To address these challenges, it’s important to leverage video conferencing, screen sharing, and collaborative project management tools. Proactively communicating your progress and questions, and establishing regular check-ins with your team, can help ensure alignment and maintain productivity in a remote setup.

What is the difference between Asic Verification Engineer Remote vs Asic Design Engineer?

AspectAsic Verification Engineer RemoteAsic Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA/ASIC verification certificationsBachelor's/Master's in Electrical Engineering or Computer Engineering; VLSI design certifications
Work EnvironmentRemote, collaborative teams, virtual toolsTypically in-office or hybrid, design labs, CAD tools
Industry UsageCommon in semiconductor, electronics, and tech companies

While both roles require a strong background in VLSI and digital design, Asic Verification Engineers focus on testing and validating ASIC designs remotely, whereas Asic Design Engineers are involved in creating and designing ASICs, often working on-site. The roles share similar credentials but differ in daily tasks and work environment.

What are the key skills and qualifications needed to thrive as an ASIC Verification Engineer remote?

To thrive as an ASIC Verification Engineer (Remote), you need a solid background in digital design, verification methodologies, and hardware description languages such as Verilog or VHDL, often supported by a degree in electrical or computer engineering. Proficiency with simulation tools (e.g., Synopsys VCS, Cadence Xcelium), scripting languages (Python, Perl), and familiarity with UVM or SystemVerilog is typically required. Strong problem-solving skills, effective communication, and the ability to work independently and collaboratively in distributed teams are valuable soft skills. These competencies are crucial for ensuring robust chip validation, efficient remote collaboration, and successful project delivery in complex hardware development environments.
What are popular job titles related to Asic Verification Engineer Remote jobs in Austin, TX? For Asic Verification Engineer Remote jobs in Austin, TX, the most frequently searched job titles are:
What job categories do people searching Asic Verification Engineer Remote jobs in Austin, TX look for? The top searched job categories for Asic Verification Engineer Remote jobs in Austin, TX are:
What cities near Austin, TX are hiring for Asic Verification Engineer Remote jobs? Cities near Austin, TX with the most Asic Verification Engineer Remote job openings:
Asic Verification Engineer Remote jobs near you
Infographic showing various Asic Verification Engineer Remote job openings in Austin, TX as of August 2026, with employment types broken down into 57% Full Time, and 43% Contract. Highlights an 100% Remote job distribution, with an average salary of $154,705 per year, or $74.4 per hour.

Design Verification Engineer (remote position)

Correct Designs

Austin, TX • On-site, Remote

$134K - $164K/yr

Contractor

Medical, Retirement

Re-posted 27 days ago

Job description

Design Verification Engineer
Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.
Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.
Correct Designs is NOT the typical contracting, staff augmentation firm. Our engineers have respected long term roles with generous hourly rates in excellent team environments. A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return. If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits.
We are based in Austin, Texas with clients throughout the US. There are opportunities for both in-person and remote work.
Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career.
Correct Designs uses E-Verify to confirm work status eligibility.
RESPONSIBILITIES:
  • Verify complex design blocks using equally complex SV/UVM verification environments
  • Develop and execute pre-silicon verification test plans
  • Develop directed and random verification tests to validate block and IP functionality
  • Develop verification components and tools
  • Develop verification functional coverage using industry standard coverage analysis tools/methods
  • Debug regression fails
  • Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

REQUIRED SKILLS AND EXPERIENCE:
  • 3 or more years of proven verification experience in a hardware development setting
  • Strong background in SystemVerilog and UVM verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Must be comfortable working across geographies

DESIRED SKILLS:
  • Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
  • Experience in other related domains such as formal verification, RTL design, or software development

EDUCATION:
Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

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