ASIC Design Engineer (eInfochips) Role: Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion Compiler and Scripting experince. What candidate will Be Doing:
ASIC Design Engineer (eInfochips) Role: Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion Compiler and Scripting experince. What candidate will Be Doing:
PCIe ASIC Design Engineer
Austin, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
PCIe ASIC Design Engineer
Austin, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Quick apply
Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
New
Quick apply
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
New
We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoC's and GPU's. This position offers ...
We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoC's and GPU's. This position offers ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoC's and GPU's. As part of NVIDIA's "AI for chip design" team, you will have ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoC's and GPU's. As part of NVIDIA's "AI for chip design" team, you will have ...
ASIC Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Senior ASIC Design Verification Engineer Location: Austin, TX / San Francisco, CA (Onsite/Hybrid) J ob Summary We are seeking an experienced Senior ASIC Design Verification Engineer to verify next ...
ASIC Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Senior ASIC Design Verification Engineer Location: Austin, TX / San Francisco, CA (Onsite/Hybrid) J ob Summary We are seeking an experienced Senior ASIC Design Verification Engineer to verify next ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across ...
Cellular ASIC Design Engineer
$175K - $308K/yr
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...
Cellular ASIC Design Engineer
$175K - $308K/yr
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...
Cellular ASIC Design Engineer
$175K - $308K/yr
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...
Cellular ASIC Design Engineer
$175K - $308K/yr
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...
Cellular ASIC Design Engineer
$175K - $308K/yr
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...
Cellular ASIC Design Engineer
$175K - $308K/yr
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Sr. Asic Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Senior ASIC Design Verification Engineer Location: Austin, TX (Onsite/Hybrid) Experience: 15+ Years Job Summary We are seeking an experienced Senior ASIC Design Verification Engineer to verify next ...
Sr. Asic Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Senior ASIC Design Verification Engineer Location: Austin, TX (Onsite/Hybrid) Experience: 15+ Years Job Summary We are seeking an experienced Senior ASIC Design Verification Engineer to verify next ...
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verifi.
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verifi.
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Austin, TX · On-site
$164K/yr
We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...
ASIC Engineer, Annapurna Labs
Austin, TX · On-site
$164K/yr
We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...
ASIC Engineer, Annapurna Labs
Austin, TX · On-site
$164K/yr
We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...
ASIC Engineer, Annapurna Labs
Austin, TX · On-site
$164K/yr
We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities ...
Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in De.
Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in De.
ASIC Hardware Design Engineer - New College Grad 2026
Austin, TX · On-site
$116 - $189.75/hr
Join the System‑On‑Chip (SOC) group as an ASIC Design Engineer to influence system‑level IP and performance across leading GPUs and SOCs. Responsibilities * Define, develop, and deliver ...
New
ASIC Hardware Design Engineer - New College Grad 2026
Austin, TX · On-site
$116 - $189.75/hr
Join the System‑On‑Chip (SOC) group as an ASIC Design Engineer to influence system‑level IP and performance across leading GPUs and SOCs. Responsibilities * Define, develop, and deliver ...
New
Asic Design Engineer information
See Austin, TX salary details
$93.2K - $102.9K
16% of jobs
$102.9K - $112.6K
3% of jobs
$112.6K - $122.4K
4% of jobs
$125.2K is the 25th percentile. Wages below this are outliers.
$122.4K - $132.1K
6% of jobs
The median wage is $138.2K / yr.
$132.1K - $141.8K
33% of jobs
$141.8K - $151.6K
3% of jobs
$151.6K - $161.3K
2% of jobs
$167.7K is the 75th percentile. Wages above this are outliers.
$161.3K - $171K
12% of jobs
$171K - $180.8K
5% of jobs
$180.8K - $190.5K
4% of jobs
$190.5K - $200.2K
12% of jobs
$93.2K
$148.9K
$200.2K
How much do asic design engineer jobs pay per year?
What is the difference between Asic Design Engineer vs FPGA Design Engineer?
| Aspect | Asic Design Engineer | FPGA Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Designing custom chips for manufacturing | Developing programmable logic designs for prototyping and deployment |
| Industry Usage | Semiconductor companies, consumer electronics, automotive | Prototyping, testing, and specialized hardware applications |
Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.
How much does an ASIC design engineer make?
What are some common challenges faced by ASIC design engineers during the design and verification phases?
Are ASIC design engineers in demand?
What are the key skills and qualifications needed to thrive as an ASIC design engineer, and why are they important?
What is an ASIC design engineer?
What does an ASIC design engineer do?
An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.

Full-time
Posted 29 days ago
Job description
Job Description:
Role: Asic Design Engineer
Location: Mountain View CA (Remote)
Note: Seeking candidate with Fusion Compiler and Scripting experince.
What candidate will Be Doing:
- Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
- Experience with high speed PCIe designs and protocols.
- Experience with Industry standard interface protocols such as AXI, APB, etc.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of Computer Architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl etc.
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- Proficiency with UPF (Low power intent)
- Proficiency in clock crossing techniques.
- Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
What we are looking for:
- Good in understanding RTL Design and Digital concepts
- Strong experience with EDA tools: Fusion Compiler, CDC
- Scripting: Pearl, Python, TCL
- At-least 5+ years of experience in Verilog Design
- AMBA AXI bus along-with ARM or C based processor
- Ensure customer satisfaction.
- Reporting to customers on daily or weekly progress effectively
Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.
Location: Mountain View CA (Remote)
About eInfochips:
eInfochips, an Arrow company (Fortune#154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across
various industries & verticals.
Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries C verticals.
EEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.
Location:US-CA-Mountain View, California (Google)
Time Type:Full time
Job Category:Engineering ServicesEEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)
All Arrow job postings are for existing job vacancies. We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.