ZipRecruiter

Log In

2

Asic Verification Engineer Remote Jobs (NOW HIRING)

Capgemini

ASIC Verification Engineer

Seattle, WA · On-site +1

$76.20K - $187.74K/yr

The role is 100% remote role About the role We are seeking an ASIC Verification Engineer with hands‐on experience working on ARM‐related IPs such as CPU (Cortex‐A v9 architecture), GPU (Mali ...

Broadcom

ASIC Verification Engineer

Irvine, CA · On-site +1

$91K - $146K/yr

ASIC Verification EngineerHigh Speed Interconnect Product (HSIP) Group TheOpportunity Broadcom is ... As a member of this elite engineering team, you won't just be "testing code"-you will be verifying ...

next page

Showing results 1-20

People also search for

All JobsAsic Verification Engineer Remote Jobs

Asic Verification Engineer Remote information

See salary details

$88K

$156.1K

$207K

How much do asic verification engineer remote jobs pay per year?

As of May 29, 2026, the average yearly pay for asic verification engineer remote in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Verification Engineer (Remote), and why are they important?

To thrive as an ASIC Verification Engineer (Remote), you need a solid background in digital design, verification methodologies, and hardware description languages such as Verilog or VHDL, often supported by a degree in electrical or computer engineering. Proficiency with simulation tools (e.g., Synopsys VCS, Cadence Xcelium), scripting languages (Python, Perl), and familiarity with UVM or SystemVerilog is typically required. Strong problem-solving skills, effective communication, and the ability to work independently and collaboratively in distributed teams are valuable soft skills. These competencies are crucial for ensuring robust chip validation, efficient remote collaboration, and successful project delivery in complex hardware development environments.

What are the main challenges of working remotely as an ASIC Verification Engineer, and how can they be addressed?

One of the main challenges of working remotely as an ASIC Verification Engineer is effective collaboration with design and verification teams, especially when debugging complex issues that benefit from real-time, face-to-face communication. Additionally, accessing hardware labs or simulation environments may require coordination with on-site colleagues. To address these challenges, it’s important to leverage video conferencing, screen sharing, and collaborative project management tools. Proactively communicating your progress and questions, and establishing regular check-ins with your team, can help ensure alignment and maintain productivity in a remote setup.

What does an ASIC Verification Engineer do?

An ASIC Verification Engineer is responsible for ensuring that an Application-Specific Integrated Circuit (ASIC) design functions as intended before it is manufactured. They develop and implement test plans, create verification environments using hardware description and verification languages like SystemVerilog or UVM, and run simulations to detect design flaws. Working remotely, these engineers collaborate with design teams using digital tools and communication platforms to review specifications, debug issues, and validate functionality. Their work is critical to reducing errors, saving costs, and ensuring high-quality chip production.

What is the difference between Asic Verification Engineer Remote vs Asic Design Engineer?

AspectAsic Verification Engineer RemoteAsic Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA/ASIC verification certificationsBachelor's/Master's in Electrical Engineering or Computer Engineering; VLSI design certifications
Work EnvironmentRemote, collaborative teams, virtual toolsTypically in-office or hybrid, design labs, CAD tools
Industry UsageCommon in semiconductor, electronics, and tech companies

While both roles require a strong background in VLSI and digital design, Asic Verification Engineers focus on testing and validating ASIC designs remotely, whereas Asic Design Engineers are involved in creating and designing ASICs, often working on-site. The roles share similar credentials but differ in daily tasks and work environment.

More about Asic Verification Engineer Remote jobs
What cities are hiring for Asic Verification Engineer Remote jobs? Cities with the most Asic Verification Engineer Remote job openings:
What are the most commonly searched types of Asic Verification Engineer jobs? The most popular types of Asic Verification Engineer jobs are:
What states have the most Asic Verification Engineer Remote jobs? States with the most job openings for Asic Verification Engineer Remote jobs include:
What job categories do people searching Asic Verification Engineer Remote jobs look for? The top searched job categories for Asic Verification Engineer Remote jobs are:
Asic Verification Engineer Remote jobs near you
Infographic showing various Asic Verification Engineer Remote job openings in the United States as of May 2026, with employment types broken down into 67% Full Time, and 33% Part Time. Highlights an 100% Remote job distribution, with an average salary of $156,077 per year, or $75 per hour.

Remote ASIC Verification Engineer (ARM IP Focus)

Capgemini Engineering

Seattle, WA • Remote

Full-time

Posted 28 days ago

Job description

A leading engineering services firm is seeking an experienced ASIC Verification Engineer to contribute to the development of cutting-edge technology solutions. This 100% remote role requires proficiency in ARM-related IPs, verification methodologies, and strong interpersonal skills. Responsibilities include overseeing the verification process, collaborating with global teams, and ensuring high-quality design outcomes.

The position offers competitive compensation and a comprehensive benefits package, allowing for personal growth and professional development. J-18808-Ljbffr

Apply