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Associate Asic Verification Engineer Jobs (NOW HIRING)

Technical Link

We are seeking a Senior / Principal Verification Engineer to lead verification architecture and execution for a next-generation scale-up switch ASIC (~500mm , TSMC 3nm/2nm). This role is critical to ...

Nvidia

ASIC Verification Engineer

Santa Clara, CA · Hybrid

NVIDIA is seeking an outstanding ASIC Verification Engineer to verify the design and implementation of the world's leading SoC's and GPU's. This position offers the opportunity to have a real impact ...

Capgemini Engineering

ASIC Verification Engineer

Seattle, WA · On-site

$76.20K - $187.74K/yr

ASIC verification Engineer The role is 100% remote role About the job you're considering We are seeking an ASIC Verification Engineer with hands-on experience working on ARM-related IPs such as CPU ...

United Airlines

ASIC Verification Engineer

Seattle, WA

$76.20K - $187.74K/yr

ASIC verification Engineer The role is 100% remote role About the job you're considering We are seeking an ASIC Verification Engineer with handson experience working on ARMrelated IPs such as CPU ...

Capgemini

ASIC Verification Engineer

Seattle, WA · On-site +1

$76.20K - $187.74K/yr

ASIC Verification Engineer At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most ...

Nvidia

Senior ASIC Verification Engineer

Madison, AL · On-site

NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company ...

Nvidia

Senior ASIC Verification Engineer

Durham, NC

NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company ...

Nvidia

Senior ASIC Verification Engineer

Hillsboro, OR · On-site

NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company ...

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$105.5K

$149.2K

$167K

How much do associate asic verification engineer jobs pay per year?

As of May 29, 2026, the average yearly pay for associate asic verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Associate Asic Verification Engineer vs Digital Design Engineer?

AspectAssociate Asic Verification EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of verification toolsBachelor's or higher in Electrical Engineering or Computer Engineering; focus on digital circuit design
Work EnvironmentVerification teams within semiconductor or tech companies, using simulation and verification toolsDesign teams creating digital circuits, using HDL languages like VHDL or Verilog
Employer & Industry UsageCommon in semiconductor, electronics, and tech companiesPrevalent in semiconductor, consumer electronics, and hardware development firms

The Associate Asic Verification Engineer primarily focuses on verifying ASIC designs through simulation and testing, ensuring functionality and performance. In contrast, the Digital Design Engineer is responsible for designing digital circuits and implementing hardware logic. Both roles require a strong background in digital electronics, but verification emphasizes testing and validation, while design emphasizes creation and implementation of digital systems.

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Associate Asic Verification Engineer jobs near you

ASIC Verification Engineer

Technical Link

On-site

Other

Posted 21 days ago

Job description

We are seeking a Senior / Principal Verification Engineer to lead verification architecture
and execution for a next-generation scale-up switch ASIC (~500mm , TSMC 3nm/2nm).
This role is critical to ensuring first-pass silicon success for a high-bandwidth, low-latency
interconnect targeting AI and HPC systems.


Key Responsibilities

  • Define full-chip and subsystem verification strategy
  • Architect scalable UVM environments
  • Develop SystemVerilog/UVM testbenches
  • Define and drive coverage closure
  • Verify high-speed protocols and switch fabrics
  • Lead debug across RTL and system level
  • Integrate VIP and models
  • Mentor team and enforce best practices


Required Qualifications

  • 12 20+ years ASIC verification experience
  • Strong expertise in SystemVerilog and UVM
  • Experience with large SoC or switch ASICs
  • Strong debugging and coverage closure skills
  • Experience with automation and regression infrastructure


Preferred

  • Experience with networking / interconnect chips
  • Experience with emulation platforms
  • Experience with very large ASIC


Location
Ottawa, Canada, preferred. Hybrid possible depending on the candidate.

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