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Associate Asic Verification Engineer Jobs in Indiana

Principal FPGA Engineer

Fort Wayne, IN ยท On-site

$137K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Principal FPGA Engineer

Wayne, IN ยท On-site

$123K - $150K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Principal FPGA Engineer

Fort Wayne, IN

$137K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Wayne, IN ยท On-site

$115K - $148K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... implementation and verification using Verilog/VHDL * 5+ years of experience with FPGAs with ...

Senior FPGA Design Engineer

Fort Wayne, IN

$121K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

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Associate Asic Verification Engineer information

What is the difference between Associate Asic Verification Engineer vs Digital Design Engineer?

AspectAssociate Asic Verification EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of verification toolsBachelor's or higher in Electrical Engineering or Computer Engineering; focus on digital circuit design
Work EnvironmentVerification teams within semiconductor or tech companies, using simulation and verification toolsDesign teams creating digital circuits, using HDL languages like VHDL or Verilog
Employer & Industry UsageCommon in semiconductor, electronics, and tech companiesPrevalent in semiconductor, consumer electronics, and hardware development firms

The Associate Asic Verification Engineer primarily focuses on verifying ASIC designs through simulation and testing, ensuring functionality and performance. In contrast, the Digital Design Engineer is responsible for designing digital circuits and implementing hardware logic. Both roles require a strong background in digital electronics, but verification emphasizes testing and validation, while design emphasizes creation and implementation of digital systems.

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What cities in Indiana are hiring for Associate Asic Verification Engineer jobs? Cities in Indiana with the most Associate Asic Verification Engineer job openings:
Infographic showing various Associate Asic Verification Engineer job openings in Indiana as of June 2026, with employment types broken down into 39% Full Time, 59% Part Time, and 2% Contract. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution.

Principal FPGA/ASIC Verification Engineer (Onsite)

Prattwhitney

Fort Wayne, IN โ€ข On-site

$90 - $120/hr

Other

Posted 2 days ago

New


Job description

Position Overview

Principal Electrical or Computer Engineer โ€“ Onsite, FortWayne, IN (USโ€‘Citizen required). Requires an active and transferable U.S. governmentโ€‘issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of highโ€‘performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.

Responsibilities
  • Verification environment architecture and design using SystemVerilog with OVM/UVM
  • Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the groupโ€™s ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams, breaking down work, planning activities, and reporting status
Qualifications
  • Typically requires a STEM degree and minimum 8years of relevant experience, or an advanced degree and minimum 5years of experience
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment (at least 4years)
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience with chipโ€‘level verification methodologies (constrainedโ€‘random testing, functional coverage analysis, assertionโ€‘based verification)
  • Experience using revision control systems such as Git or Subversion
  • Demonstrated ability to work independently and mentor junior engineers
  • Preferred: Experience with ASIC/FPGA lab validation and debug, familiarity with DFT, manufacturability, and production test concepts, proficiency with Unix/Linux, scripting or software development
Security Clearance

U.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.

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