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Internship Asic Verification Engineer Jobs in Indiana

Principal FPGA Engineer

Fort Wayne, IN

$137K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Principal FPGA Engineer

Fort Wayne, IN ยท On-site

$137K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Fort Wayne, IN ยท On-site

$128K - $164K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Principal FPGA Engineer

Wayne, IN ยท On-site

$123K - $150K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Wayne, IN ยท On-site

$115K - $148K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... implementation and verification using Verilog/VHDL * 5+ years of experience with FPGAs with ...

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Internship Asic Verification Engineer information

What does an internship ASIC verification engineer do?

An Internship ASIC Verification Engineer assists in verifying the functionality and performance of ASIC (Application-Specific Integrated Circuit) designs before they are manufactured. This role typically involves creating and running testbenches, writing verification code (often in SystemVerilog or similar languages), and collaborating with design engineers to identify and resolve issues. Interns learn industry-standard verification methodologies, such as UVM, and gain hands-on experience with simulation tools and debugging processes. The goal is to ensure the ASIC design meets specifications and is free of critical errors before fabrication.

What types of projects and responsibilities can an internship ASIC verification engineer expect to work on during their internship?

As an Internship ASIC Verification Engineer, you will typically assist in developing verification environments, writing testbenches, and executing test cases to validate the functionality of ASIC designs. You may work with simulation tools, debug issues alongside experienced engineers, and contribute to documentation and coverage analysis. Interns are often included in team meetings and code reviews, providing hands-on exposure to industry-standard verification methodologies and collaborative workflows. This experience helps build a strong foundation for future roles in hardware design and verification.

What are the key skills and qualifications needed to thrive as an internship ASIC verification engineer, and why are they important?

To thrive as an Internship ASIC Verification Engineer, you need a solid background in digital design fundamentals, hardware description languages (like Verilog or VHDL), and coursework in computer engineering or a related field. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages (like Python or Perl), and possibly exposure to UVM methodology are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help interns adapt and contribute quickly. These competencies ensure accurate verification processes, minimize design flaws, and support successful project outcomes in collaborative engineering environments.

What is the difference between Internship Asic Verification Engineer vs Asic Verification Engineer?

AspectInternship Asic Verification EngineerAsic Verification Engineer
QualificationsEnrolled in or recent graduate of relevant engineering programsBachelor's or Master's in Electrical Engineering or related field
Work EnvironmentInternship, supervised, part-time or full-timeFull-time professional role in design teams
ResponsibilitiesAssist verification tasks, learn tools and processesDesign, develop, and execute verification plans independently
Experience LevelEntry-level, limited industry experienceMid-level, with practical verification experience

In summary, an Internship Asic Verification Engineer is a temporary, learning-focused role for students or recent graduates, while an Asic Verification Engineer is a full-time professional responsible for verification tasks within the industry.

What are the most commonly searched types of Asic Verification Engineer jobs in Indiana?

The most popular types of Asic Verification Engineer jobs in Indiana are:

What are popular job titles related to Internship Asic Verification Engineer jobs in Indiana?

For Internship Asic Verification Engineer jobs in Indiana, the most frequently searched job titles are:

What cities in Indiana are hiring for Internship Asic Verification Engineer jobs?

Cities in Indiana with the most Internship Asic Verification Engineer job openings:

Infographic showing various Internship Asic Verification Engineer job openings in Indiana as of August 2026, with employment types broken down into 67% Internship, and 33% Full Time. Highlights an 67% In-person, and 33% Hybrid job distribution.

Principal FPGA/ASIC Verification Engineer (Onsite)

Prattwhitney

Fort Wayne, IN โ€ข On-site

$90 - $120/hr

Other

Posted 18 days ago


Job description

Position Overview

Principal Electrical or Computer Engineer โ€“ Onsite, FortWayne, IN (USโ€‘Citizen required). Requires an active and transferable U.S. governmentโ€‘issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of highโ€‘performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.

Responsibilities
  • Verification environment architecture and design using SystemVerilog with OVM/UVM
  • Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the groupโ€™s ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams, breaking down work, planning activities, and reporting status
Qualifications
  • Typically requires a STEM degree and minimum 8years of relevant experience, or an advanced degree and minimum 5years of experience
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment (at least 4years)
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience with chipโ€‘level verification methodologies (constrainedโ€‘random testing, functional coverage analysis, assertionโ€‘based verification)
  • Experience using revision control systems such as Git or Subversion
  • Demonstrated ability to work independently and mentor junior engineers
  • Preferred: Experience with ASIC/FPGA lab validation and debug, familiarity with DFT, manufacturability, and production test concepts, proficiency with Unix/Linux, scripting or software development
Security Clearance

U.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.

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