Lafayette, IN · On-site
Debug RTL, simulation, and MBIST integration issues. * Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure. * Work closely ...
Quick apply
Lafayette, IN · On-site
Debug RTL, simulation, and MBIST integration issues. * Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure. * Work closely ...
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Wayne, IN · On-site
$92K - $124K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Wayne, IN · On-site
$92K - $124K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Fort Wayne, IN · On-site
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/orSystemVerilog * Familiarity with best practice chip-level verification ...
Fort Wayne, IN · On-site
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/orSystemVerilog * Familiarity with best practice chip-level verification ...
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Wayne, IN · On-site
$109K - $150K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
Wayne, IN · On-site
$109K - $150K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
Wayne, IN · On-site
$92K - $124K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Wayne, IN · On-site
$92K - $124K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Fort Wayne, IN · On-site
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Fort Wayne, IN · On-site
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Fort Wayne, IN · On-site
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Fort Wayne, IN · On-site
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Fort Wayne, IN · On-site
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
Fort Wayne, IN · On-site
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
Fort Wayne, IN · On-site
$102K - $138K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Fort Wayne, IN · On-site
$102K - $138K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Fort Wayne, IN · On-site
$102K - $138K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Fort Wayne, IN · On-site
$102K - $138K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Lafayette, IN · On-site
$125K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Indianapolis, IN · On-site
$124K - $159K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Indianapolis, IN · On-site
$124K - $159K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
$76.6K - $85.4K
0% of jobs
$85.4K - $94.2K
0% of jobs
$94.2K - $103.1K
1% of jobs
$103.1K - $111.9K
0% of jobs
$111.9K - $120.7K
0% of jobs
$124.4K is the 25th percentile. Wages below this are outliers.
$120.7K - $129.5K
57% of jobs
$133.3K is the 75th percentile. Wages above this are outliers.
$129.5K - $138.4K
38% of jobs
$138.4K - $147.2K
0% of jobs
$147.2K - $156K
1% of jobs
$156K - $164.8K
1% of jobs
$164.8K - $173.7K
1% of jobs
$76.6K
$132.6K
$173.7K
| Aspect | Rtl | Speech-Language Pathologist |
|---|---|---|
| Required Credentials | Typically certification or training in Rtl techniques | Master's degree in Speech-Language Pathology, state licensure, ASHA certification |
| Work Environment | Educational, clinical, or therapy settings focusing on communication skills | Hospitals, schools, clinics, private practice |
| Industry Usage | Used in therapy and communication improvement programs | Healthcare and educational sectors specializing in speech and language disorders |
While Rtl (Response to Intervention) is a framework used to support students with learning and communication challenges, a Speech-Language Pathologist is a licensed professional who diagnoses and treats speech and language disorders. Rtl often guides intervention strategies, whereas Speech-Language Pathologists provide direct therapy and assessments. Both roles are integral in communication development but differ in credentials and scope of practice.
For Rtl jobs in Indiana, the most frequently searched job titles are:
The top searched job categories for Rtl jobs in Indiana are:
Full-time
Posted 19 days ago
Role: CMM Programmer
Location: Remote- Must be working as per PST time zone
Duration: Contract (Full-Time)
Job Description:
We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.
Responsibilities:
• Perform MBIST insertion for complex SoC designs using Synopsys SMS.
• Integrate and verify MBIST at the top level.
• Develop, execute, and debug MBIST simulations using Synopsys VCS, including:
– RTL
– No-delay gate level simulations
– With-delay (timing-aware) simulations
• Generate and validate MBIST test patterns using Vecgen.
• Debug RTL, simulation, and MBIST integration issues.
• Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure.
• Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.
• Drive issue resolution independently and document implementation flows and debug findings.
Required Qualifications:
8+ years of hands-on DFT experience, with significant focus on MBIST.
• Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.
• Proficiency with Synopsys VCS for MBIST verification and simulation.
• Deep understanding of the complete MBIST flow:
– MBIST insertion
– Top-level integration
– Verification
– Pattern generation (Vecgen)
– Diagnostics
– Simulation and debug
• Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).
• Experience running and debugging:
– No-delay simulations
Cisco Confidential
– With-delay simulations
• Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
• Strong debugging and root-cause analysis skills across RTL, MBIST, and simulation environments.
• Ability to work independently with minimal supervision.
• Experience with large, complex SoC designs containing multiple memory instances.
• Familiarity with Verilog/SystemVerilog and standard DFT methodologies.
Preferred Qualifications:
• Experience with advanced SoC DFT integration.
• Familiarity with ATPG and scan insertion flows.
• Experience with scripting (Tcl, Perl, or Python) to automate MBIST flows and debug.
• Experience working in fast-paced semiconductor product development.
Key Skills:
• Synopsys MBIST (SMS5/SMS6)
• Synopsys VCS
• MBIST insertion
• Top-level MBIST verification
• VecGen pattern generation
• MBIST diagnostics
• MBIST repair schemes and memory test algorithms
• No-delay, with-delay simulation and debug
• Silicon bring-up and post-silicon debug
• SoC DFT integration
• Tcl / Perl / Python scripting
• Strong communication skills
• Self-motivated and capable of working independently
Ideal Candidate:
The ideal contractor is a senior, hands-on MBIST engineer who can quickly become productive with minimal ramp-up. They should have deep experience with Synopsys SMS and VCS, excellent debugging skills, strong communication abilities, and a proven track record of independently delivering MBIST implementation, verification, and debug for complex SoC designs.
