Fort Wayne, IN · On-site
$90 - $120/hr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA verification flow
Fort Wayne, IN · On-site
$90 - $120/hr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA verification flow
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Fort Wayne, IN · On-site
$150 - $200/hr
Capture requirements and design digital ASIC/FPGA architecture, including RTL development, timing analysis, closure, verification, and system integration. * Identify and implement tools ...
Fort Wayne, IN · On-site
$150 - $200/hr
Capture requirements and design digital ASIC/FPGA architecture, including RTL development, timing analysis, closure, verification, and system integration. * Identify and implement tools ...
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Fort Wayne, IN · On-site
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Wayne, IN · On-site
$109K - $150K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Wayne, IN · On-site
$92K - $124K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Wayne, IN · On-site
$92K - $124K/yr
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Fort Wayne, IN · On-site
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/orSystemVerilog * Familiarity with best practice chip-level verification ...
Fort Wayne, IN · On-site
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/orSystemVerilog * Familiarity with best practice chip-level verification ...
Wayne, IN · On-site
$92K - $124K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Wayne, IN · On-site
$92K - $124K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Wayne, IN · On-site
$109K - $150K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
Wayne, IN · On-site
$109K - $150K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
$121K - $167K/yr
RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog * Familiarity with best practice chip-level verification ...
Fort Wayne, IN · On-site
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Fort Wayne, IN · On-site
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
$102K - $138K/yr
At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL. * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration * Drive continuous improvement by identifying and ...
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
$121K - $167K/yr
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical ...
Zionsville, IN · On-site
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Zionsville, IN · On-site
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Lafayette, IN · On-site
$125K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
$76.6K - $85.4K
0% of jobs
$85.4K - $94.2K
0% of jobs
$94.2K - $103.1K
1% of jobs
$103.1K - $111.9K
0% of jobs
$111.9K - $120.7K
0% of jobs
$124.4K is the 25th percentile. Wages below this are outliers.
$120.7K - $129.5K
57% of jobs
$133.3K is the 75th percentile. Wages above this are outliers.
$129.5K - $138.4K
38% of jobs
$138.4K - $147.2K
0% of jobs
$147.2K - $156K
1% of jobs
$156K - $164.8K
1% of jobs
$164.8K - $173.7K
1% of jobs
$76.6K
$132.6K
$173.7K
| Aspect | Rtl | Speech-Language Pathologist |
|---|---|---|
| Required Credentials | Typically certification or training in Rtl techniques | Master's degree in Speech-Language Pathology, state licensure, ASHA certification |
| Work Environment | Educational, clinical, or therapy settings focusing on communication skills | Hospitals, schools, clinics, private practice |
| Industry Usage | Used in therapy and communication improvement programs | Healthcare and educational sectors specializing in speech and language disorders |
While Rtl (Response to Intervention) is a framework used to support students with learning and communication challenges, a Speech-Language Pathologist is a licensed professional who diagnoses and treats speech and language disorders. Rtl often guides intervention strategies, whereas Speech-Language Pathologists provide direct therapy and assessments. Both roles are integral in communication development but differ in credentials and scope of practice.
$90 - $120/hr
Other
Posted 5 days ago
Principal Electrical or Computer Engineer – Onsite, FortWayne, IN (US‑Citizen required). Requires an active and transferable U.S. government‑issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of high‑performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.
ResponsibilitiesU.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.
EEO StatementRTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.
