FPGA Engineer
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
$125K - $161K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
$125K - $160K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
$125K - $160K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Lafayette, IN · On-site
$125K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Lafayette, IN · On-site
$125K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Indianapolis, IN · On-site
$124K - $159K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Indianapolis, IN · On-site
$124K - $159K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept ...
Indianapolis, IN · On-site
$132K - $162K/yr
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools * Expertise achieving timing closure on FPGA designs and ...
Indianapolis, IN · On-site
$132K - $162K/yr
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools * Expertise achieving timing closure on FPGA designs and ...
Indianapolis, IN · Hybrid
$132K - $162K/yr
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools * Expertise achieving timing closure on FPGA designs and ...
Indianapolis, IN · Hybrid
$132K - $162K/yr
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools * Expertise achieving timing closure on FPGA designs and ...
West Lafayette, IN · Hybrid
$133K - $163K/yr
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools * Expertise achieving timing closure on FPGA designs and ...
West Lafayette, IN · Hybrid
$133K - $163K/yr
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools * Expertise achieving timing closure on FPGA designs and ...
$76.6K - $85.4K
0% of jobs
$85.4K - $94.2K
0% of jobs
$94.2K - $103.1K
1% of jobs
$103.1K - $111.9K
0% of jobs
$111.9K - $120.7K
0% of jobs
$124.4K is the 25th percentile. Wages below this are outliers.
$120.7K - $129.5K
57% of jobs
$133.3K is the 75th percentile. Wages above this are outliers.
$129.5K - $138.4K
38% of jobs
$138.4K - $147.2K
0% of jobs
$147.2K - $156K
1% of jobs
$156K - $164.8K
1% of jobs
$164.8K - $173.7K
1% of jobs
$76.6K
$132.6K
$173.7K
| Aspect | Rtl | Speech-Language Pathologist |
|---|---|---|
| Required Credentials | Typically certification or training in Rtl techniques | Master's degree in Speech-Language Pathology, state licensure, ASHA certification |
| Work Environment | Educational, clinical, or therapy settings focusing on communication skills | Hospitals, schools, clinics, private practice |
| Industry Usage | Used in therapy and communication improvement programs | Healthcare and educational sectors specializing in speech and language disorders |
While Rtl (Response to Intervention) is a framework used to support students with learning and communication challenges, a Speech-Language Pathologist is a licensed professional who diagnoses and treats speech and language disorders. Rtl often guides intervention strategies, whereas Speech-Language Pathologists provide direct therapy and assessments. Both roles are integral in communication development but differ in credentials and scope of practice.

Apply Now
RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, FPGA verification tools, reverse engineering, cocotb, pyuvm
Full Time
Travel required to 10%.
Must be able to apply for and maintain a U.S. Government Security Clearance
FPGA Engineer
The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications.
Key Responsibilities
FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest in leakage-resilient hardware cryptography algorithms using state-of-the-art FPGA hardware.
Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment.
Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software-based testing solutions where applicable to validate FPGA designs.
Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks.
Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment.
System Integration: Ensure seamless integration between internally-developed and third-party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system-level architecture.
Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms.
Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance.
Continuous Learning: Actively stay up-to-date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities.
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Guided missile and space vehicle manufacturing
11 - 50 Employees
Washington, DC, US
2013