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Fpga Uvm Verification Engineer Jobs in Indiana (NOW HIRING)

Raytheon Technologies

FPGA Engineer II

Fort Wayne, IN · On-site

$128K - $164K/yr

The MPD department is seeking an FPGA Engineer II to join our team. In this role, you will leverage ... Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis ...

Raytheon

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

The MPD department is seeking an FPGA Engineer II to join our team. In this role, you will leverage ... Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis ...

Raytheon Technologies

FPGA Engineer II

Wayne, IN · On-site

$115K - $148K/yr

The MPD department is seeking an FPGA Engineer II to join our team. In this role, you will leverage ... Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis ...

Raytheon Technologies

Senior FPGA Design Engineer

Wayne, IN · On-site

$109K - $150K/yr

The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you ... Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis ...

Raytheon

Senior FPGA Design Engineer

Fort Wayne, IN

$121K - $167K/yr

The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you ... Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis ...

Raytheon Technologies

Principal FPGA Engineer

Wayne, IN · On-site

$123K - $150K/yr

The MPD department is seeking a Principal FPGA Engineer to join our team. In this role, you will ... Constrained random verification in UVM using System Verilog * Verification utilizing emulation ...

Raytheon

Principal FPGA Engineer

Fort Wayne, IN

$137K - $167K/yr

The MPD department is seeking a Principal FPGA Engineer to join our team. In this role, you will ... Constrained random verification in UVM using System Verilog * Verification utilizing emulation ...

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Fpga Uvm Verification Engineer information

What are some common challenges faced by FPGA UVM Verification Engineers during project cycles?

FPGA UVM Verification Engineers often encounter challenges such as meeting tight verification deadlines, adapting to evolving specifications, and debugging complex functional issues in large-scale designs. Collaboration with design engineers is critical to resolve ambiguities and ensure comprehensive test coverage. Staying up-to-date with the latest UVM methodologies and maintaining reusable verification environments are also key aspects that require continuous learning and adaptability.

What is an FPGA UVM Verification Engineer?

FPGA UVM Verification Engineers are specialized professionals who verify and validate the functionality of Field Programmable Gate Arrays (FPGAs) using the Universal Verification Methodology (UVM). Their role involves creating testbenches and simulation environments to ensure that FPGA designs meet their specifications and operate reliably. They use hardware description languages like Verilog or VHDL and apply advanced verification techniques to identify and resolve design issues early in the development process. Their expertise is crucial for delivering high-quality, error-free FPGA products for applications in industries such as telecommunications, automotive, and aerospace.

What is the difference between Fpga Uvm Verification Engineer vs FPGA Verification Engineer?

AspectFpga Uvm Verification EngineerFPGA Verification Engineer
Primary FocusUVM-based verification of FPGA designsGeneral FPGA design and verification
Skills & CertificationsUVM, SystemVerilog, FPGA toolsVerilog/VHDL, FPGA tools, verification skills
Work EnvironmentVerification teams, simulation environmentsDesign and verification teams, FPGA labs
Industry UsageHigh in verification-heavy projectsBroad, including design and verification

The Fpga Uvm Verification Engineer specializes in UVM-based verification methodologies for FPGA designs, focusing on creating testbenches and simulation environments. In contrast, the FPGA Verification Engineer may handle broader verification tasks, including both design and testing. Both roles require knowledge of FPGA tools and verification languages, but the UVM Verification Engineer emphasizes UVM and SystemVerilog expertise for verification processes.

What are the key skills and qualifications needed to thrive as an FPGA UVM Verification Engineer?

To excel as an FPGA UVM Verification Engineer, you need a solid background in digital design, verification methodologies, and a degree in electrical or computer engineering. Expertise with SystemVerilog, Universal Verification Methodology (UVM), and simulation tools like ModelSim or Questa is typically required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills that set top candidates apart. These skills ensure accurate and efficient verification of complex FPGA designs, leading to robust and reliable hardware products.
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Fpga Uvm Verification Engineer jobs near you

Principal FPGA/ASIC Verification Engineer (Onsite)

Prattwhitney

Fort Wayne, IN • On-site

$90 - $120/hr

Other

Posted 7 days ago

Job description

Position Overview

Principal Electrical or Computer Engineer – Onsite, FortWayne, IN (US‑Citizen required). Requires an active and transferable U.S. government‑issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of high‑performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.

Responsibilities
  • Verification environment architecture and design using SystemVerilog with OVM/UVM
  • Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group’s ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams, breaking down work, planning activities, and reporting status
Qualifications
  • Typically requires a STEM degree and minimum 8years of relevant experience, or an advanced degree and minimum 5years of experience
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment (at least 4years)
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience with chip‑level verification methodologies (constrained‑random testing, functional coverage analysis, assertion‑based verification)
  • Experience using revision control systems such as Git or Subversion
  • Demonstrated ability to work independently and mentor junior engineers
  • Preferred: Experience with ASIC/FPGA lab validation and debug, familiarity with DFT, manufacturability, and production test concepts, proficiency with Unix/Linux, scripting or software development
Security Clearance

U.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.

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