Experience with advanced verification environments such as UVM & OVM * Experience using System Verilog for verification * Build FPGAs with difficult timing and/or difficult routing constraints
Experience with advanced verification environments such as UVM & OVM * Experience using System Verilog for verification * Build FPGAs with difficult timing and/or difficult routing constraints
Roving Utility Forester
Terre Haute, IN · On-site
$20/hr
ACRT, Inc. Full time Regular ACRT, Inc. is the largest and most trusted independent UVM consulting and training company in the nation, and we're growing! We are seeking new Ready Force employees ...
Roving Utility Forester
Terre Haute, IN · On-site
$20/hr
ACRT, Inc. Full time Regular ACRT, Inc. is the largest and most trusted independent UVM consulting and training company in the nation, and we're growing! We are seeking new Ready Force employees ...
Roving Utility Forester
Terre Haute, IN · On-site
$20/hr
ACRT, Inc. Full time Regular ACRT, Inc. is the largest and most trusted independent UVM consulting and training company in the nation, and we're growing! We are seeking new Ready Force employees ...
Roving Utility Forester
Terre Haute, IN · On-site
$20/hr
ACRT, Inc. Full time Regular ACRT, Inc. is the largest and most trusted independent UVM consulting and training company in the nation, and we're growing! We are seeking new Ready Force employees ...
Principal FPGA Engineer with Security Clearance
Fort Wayne, IN · On-site
$128K - $156K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
Principal FPGA Engineer with Security Clearance
Fort Wayne, IN · On-site
$128K - $156K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
FPGA Engineer II
Wayne, IN · On-site
$115K - $148K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
FPGA Engineer II
Wayne, IN · On-site
$115K - $148K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
Senior Specialist, Electrical Engineering (FPGA Design Engineer)
Fort Wayne, IN · On-site
$102K - $138K/yr
Experience with advanced verification environments such as UVM & OVM * Experience using System Verilog for verification * Build FPGAs with difficult timing and/or difficult routing constraints
Senior Specialist, Electrical Engineering (FPGA Design Engineer)
Fort Wayne, IN · On-site
$102K - $138K/yr
Experience with advanced verification environments such as UVM & OVM * Experience using System Verilog for verification * Build FPGAs with difficult timing and/or difficult routing constraints
FPGA Engineer II with Security Clearance
Fort Wayne, IN · On-site
$113K - $156K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
FPGA Engineer II with Security Clearance
Fort Wayne, IN · On-site
$113K - $156K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
Principal FPGA Engineer
$137K - $167K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
Principal FPGA Engineer
$137K - $167K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
Senior FPGA Design Engineer
Wayne, IN · On-site
$109K - $150K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Senior FPGA Design Engineer
Wayne, IN · On-site
$109K - $150K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Principal FPGA Engineer
Wayne, IN · On-site
$123K - $150K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
Principal FPGA Engineer
Wayne, IN · On-site
$123K - $150K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
FPGA Engineer II
Fort Wayne, IN · On-site
$128K - $164K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
FPGA Engineer II
Fort Wayne, IN · On-site
$128K - $164K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
Principal FPGA Engineer
Fort Wayne, IN · On-site
$137K - $167K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
Principal FPGA Engineer
Fort Wayne, IN · On-site
$137K - $167K/yr
Constrained random verification in UVM using System Verilog * Verification utilizing emulation platforms, such as Veloce * Experience with High Level Synthesis (HLS) * Experience with vector ...
Senior FPGA Design Engineer
Fort Wayne, IN · On-site
$121K - $167K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Senior FPGA Design Engineer
Fort Wayne, IN · On-site
$121K - $167K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
FPGA Engineer II
$128K - $164K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
FPGA Engineer II
$128K - $164K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Experience with timing closure, clock domain ...
Senior FPGA Design Engineer with Security Clearance
Fort Wayne, IN · On-site
$113K - $156K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Senior FPGA Design Engineer with Security Clearance
Fort Wayne, IN · On-site
$113K - $156K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Senior FPGA Design Engineer
$121K - $167K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Senior FPGA Design Engineer
$121K - $167K/yr
Constrained random verification in UVM using System Verilog * Experience with High Level Synthesis (HLS) * Experience with vector processors and/or GPUs * Demonstrated ability to lead teams to ...
Uvm information
See Indiana salary details
$64.2K - $73K
1% of jobs
$73K - $81.8K
2% of jobs
$81.8K - $90.6K
5% of jobs
$90.6K - $99.4K
11% of jobs
$102.7K is the 25th percentile. Wages below this are outliers.
$99.4K - $108.1K
16% of jobs
The median wage is $116.6K / yr.
$108.1K - $116.9K
16% of jobs
$116.9K - $125.7K
17% of jobs
$130.6K is the 75th percentile. Wages above this are outliers.
$125.7K - $134.5K
14% of jobs
$134.5K - $143.3K
11% of jobs
$143.3K - $152K
5% of jobs
$152K - $160.8K
3% of jobs
$64.2K
$118.7K
$160.8K
How much do uvm jobs pay per year?
What is the difference between Uvm vs Network Technician?
| Aspect | Uvm | Network Technician |
|---|---|---|
| Required Certifications | UVM certifications, technical training | CompTIA Network+, Cisco CCNA |
| Work Environment | Data centers, server rooms, IT departments | Office settings, client sites, data centers |
| Industry Usage | IT, data management, cloud services | Networking, telecommunications, IT support |
Uvm and Network Technicians both work in IT environments, often requiring similar certifications and working in data centers or network setups. While Uvm specialists focus on virtual machine management and cloud infrastructure, Network Technicians primarily handle network hardware, configurations, and troubleshooting. Both roles are essential in maintaining IT infrastructure but differ in their specific technical focus and daily tasks.
What are some common challenges faced by UVM (Universal Verification Methodology) engineers during verification projects?
What are UVMs in the context of job titles?
What are the key skills and qualifications needed to thrive as a uvm (University of Vermont) employee, and why are they important?

$117K - $150K/yr
Other
Posted 5 days ago
Job description
Job Title: Senior Specialist, Electrical Engineering (FPGA Digital Design Engineer)
Job Code: 38228
Job Location: Fort Wayne, IN
Job Schedule: 9/80 Regular
Job Description:
Responsible for developing FPGA Firmware in the Space & Mission Systems (SMS) Segment of L3Harris. The SMS Segment provides critical mission solutions for space and airborne domains with defense, intelligence, and commercial applications. As an FPGA design engineer, you will be directly involved in one or more of the areas of design, integration, and test of advanced satellite communication links, digital telemetry, signal processing, and/or encryption technology.
Essential Functions:
- Support proposal efforts in the estimation and planning of end-to-end FPGA development.
- Decompose and allocate system and box-level requirements to FPGA requirements and specifications.
- Architect solutions against requirements and implement those solutions in various FPGA technologies or platforms.
- Design Med/High Complexity Field Programmable Gate Array (FPGA) starting from System De-composition and completing through System Integration and Test
- Follow, enforce, and refine consistent firmware development processes across FPGA designs.
- Synthesize designs to targeted technologies and perform constraint driven place and route and analysis.
- Generate design review and deliverable documentation including review packages, block diagrams, interface control documents, and test plans/procedures.
- Conduct design peer reviews at various phases in the development process.
- Ensure FPGA simulations verify performance, then integrate and test the FPGA on the circuit card assembly.
- Generate verification plans and procedures to validate hardware.
Perform hardware testing and debug. - Ability to obtain a Secret clearance
Qualifications:
- Bachelors of Science Degree in Electrical/Computer Engineering with 6 years' professional experience or a Graduate degree and a minimum of 4 years' relevant professional experience. In lieu of a degree, minimum of 10 years' of prior related experience
- 6+ years experience using VHDL/Verilog
- 6+ years experience with and understanding of AMD Xilinx FPGA architecturesÂ
- 3+ Years of professional experience with Xilinx Vivado
- 3+ years experience performing timing closure, optimizing FPGA resource utilization
- 3+ years experience debugging down to the hardware level, using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA Debugging tools
Preferred Additional Skills:
- FPGA development and Verification Vendor tool suites: Xilinx ISE, Xilinx Vivado, Xilinx Vitis, Microchip Libero, Mentor Graphics ModelSim/Questa, Synopsis Synplicity
- Version Control tools such as GIT, SVN, CVS.
- Experience with advanced verification environments such as UVM & OVM
- Experience using System Verilog for verificationÂ
- Build FPGAs with difficult timing and/or difficult routing constraints
- Develop FPGA requirements and specifications
- FPGA Device Selection and supporting the Pinout on a new CCA Design
- High speed memory interfaces and/or high speed SERDES interfaces
- Analog to Digital (AD) and Digital to Analog (DA) interfaces
- Experience with AXI streaming and control buses
- Possess the ability to interface with Hardware, Software, and Systems Engineering
- Self-motivated individual with the ability to work and communicate effectively within a development group
- Bring-up of advanced FPGA products such as SoC, MPSoC, RFSoC, ACAP, etc.
- Digital Circuit Card Design: Schematic Entry, PCB/PWB Layout/Route, Signal Integrity Analysis.
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