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New Grad Asic Design Verification Engineer Jobs in Indiana

Sr Design Verification Engineer

Lebanon, IN ยท On-site

$130K - $159K/yr

Job Title: Sr. Design Verification Engineer Location: Remote Onsite Requirement: Approximately 1 week per month onsite at the project location in Lebanon, IN Duration: Longterm Job Summary The Sr. ...

Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... implementation and verification using Verilog/VHDL * 5+ years of experience with FPGAs with ...

FPGA Engineer II with Security Clearance

Fort Wayne, IN ยท On-site

$113K - $156K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Fort Wayne, IN ยท On-site

$128K - $164K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Wayne, IN ยท On-site

$115K - $148K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Senior FPGA Design Engineer

Fort Wayne, IN

$121K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Senior FPGA Design Engineer

Wayne, IN ยท On-site

$109K - $150K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

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New Grad Asic Design Verification Engineer information

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.
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Infographic showing various New Grad Asic Design Verification Engineer job openings in Indiana as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Sr Design Verification Engineer

Intellectt INC

Lebanon, IN โ€ข On-site

$130K - $159K/yr

Contractor

Re-posted 2 days ago


Job description

Job Title: Sr. Design Verification Engineer
Location: Remote
Onsite Requirement: Approximately 1 week per month onsite at the project location in Lebanon, IN
Duration: Longterm

Job Summary

The  Sr. Design Verification Engineer will lead and coordinate detailed design activities for a large regulated manufacturing capital project, mainly covering utilities systems, tank farm, and central infrastructure. The role ensures design quality, compliance, schedule alignment, and smooth coordination between design teams, engineering stakeholders, commissioning, qualification, and project leadership.

Key Responsibilities

  • Lead detailed design for utilities, tank farm, and infrastructure systems
  • Ensure design deliverables and IFC drawings are accurate and on schedule
  • Manage URS, design verification, and design qualification activities
  • Coordinate design reviews, RFIs, and issue resolution
  • Ensure compliance with engineering standards and regulatory requirements
  • Work with commissioning, qualification, engineering, and construction teams
  • Report design progress and key project metrics to leadership

Skills Required

  • Experience leading design for large capital projects
  • Strong knowledge of utilities, plant infrastructure, and tank farm systems
  • Hands-on experience with URS, RFIs, IFC drawings, and design qualification
  • Understanding of regulated industries like pharma, biotech, or life sciences
  • Strong coordination, communication, and problem-solving skills
  • Ability to manage schedules, stakeholders, and cross-functional teams

For more information, please reach out at 732-719-4936 or share your updated resume with padma.priya@intellectt.com.