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Asic Design Verification Engineer Internship Jobs in Indiana

Kratos Defense

ASIC Design Leader

Crane, IN

Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... implementation and verification using Verilog/VHDL * 5+ years of experience with FPGAs with ...

Rolls-Royce

Principal Engineer - FPGA/ASIC Design

West Lafayette, IN · Hybrid

$133K - $163K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Job Title: Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location ... In this technical role, you will design, verify, integrate, and test FPGA/ASIC solutions, which ...

Rolls-Royce

Principal Engineer - FPGA/ASIC Design

Indianapolis, IN · Hybrid

$132K - $162K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Job Title: Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location ... In this technical role, you will design, verify, integrate, and test FPGA/ASIC solutions, which ...

Prattwhitney

FPGA Verification Engineer II (Onsite)

Fort Wayne, IN · On-site

$90 - $130/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The role involves design, implementation, and verification of testbenches for high‑performance ... ASIC/FPGA lab validation experience with advanced lab equipment. * Design for Test (DFT) and ...

New

RTX

FPGA Engineer II with Security Clearance

Fort Wayne, IN · On-site

$113K - $156K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon

Senior FPGA Design Engineer

Fort Wayne, IN

$121K - $167K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon Technologies

FPGA Engineer II

Wayne, IN · On-site

$115K - $148K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon Technologies

Senior FPGA Design Engineer

Fort Wayne, IN · On-site

$121K - $167K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon Technologies

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon

FPGA Engineer II

Fort Wayne, IN

$128K - $164K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Raytheon Technologies

Senior FPGA Design Engineer

Wayne, IN · On-site

$109K - $150K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

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All JobsAsic Design Verification Engineer JobsAsic Design Verification Engineer Internship JobsAsic Design Verification Engineer Internship Jobs in Indiana

Asic Design Verification Engineer Internship information

What does an ASIC design verification engineer intern do?

An ASIC Design Verification Engineer Intern assists with testing and validating the functionality of Application-Specific Integrated Circuits (ASICs) during the hardware development process. Their responsibilities typically include writing test benches, developing verification environments, running simulations, and identifying bugs or design flaws before fabrication. Interns often use hardware description languages like Verilog or VHDL and verification methodologies such as UVM. This role is essential to ensure that the final ASIC design meets the required specifications and functions correctly.

What are the key skills and qualifications needed to thrive as an ASIC design verification engineer intern?

To thrive as an ASIC Design Verification Engineer Intern, you typically need a solid background in digital logic design, hardware description languages (HDLs) like Verilog or VHDL, and coursework in computer engineering or electrical engineering. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages like Python or Perl, and version control systems is highly valued. Strong analytical thinking, problem-solving abilities, and effective teamwork skills set exceptional candidates apart. These competencies are crucial for ensuring the functionality, reliability, and timely delivery of complex integrated circuits.

What are some typical challenges faced during an ASIC design verification engineer internship, and how can interns effectively address them?

Interns in ASIC design verification often encounter challenges such as understanding complex hardware specifications, learning new verification tools and methodologies, and debugging intricate design issues. To overcome these, it's important to proactively seek guidance from senior engineers, utilize available documentation and training resources, and actively participate in team meetings. Building strong communication skills and staying organized with test plans and bug tracking can also make the workflow smoother and more manageable.

What is the difference between Asic Design Verification Engineer Internship vs Asic Design Engineer?

AspectAsic Design Verification Engineer InternshipAsic Design Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's degree in Electrical Engineering or related field
Work EnvironmentInternship program, often in a corporate R&D or design teamFull-time professional role in ASIC design teams
ResponsibilitiesAssisting in verification testbenches, running simulations, learning verification toolsDesigning, implementing, and testing ASIC hardware components
DurationUsually 3-6 monthsFull-time ongoing role

The Asic Design Verification Engineer Internship is an entry-level, temporary position focused on assisting verification tasks, while the Asic Design Engineer role involves full responsibility for ASIC design and development. Internships provide hands-on experience, whereas full engineers lead projects and make design decisions.

What are popular job titles related to Asic Design Verification Engineer Internship jobs in Indiana?

For Asic Design Verification Engineer Internship jobs in Indiana, the most frequently searched job titles are:

What job categories do people searching Asic Design Verification Engineer Internship jobs in Indiana look for?

The top searched job categories for Asic Design Verification Engineer Internship jobs in Indiana are:

What cities in Indiana are hiring for Asic Design Verification Engineer Internship jobs?

Cities in Indiana with the most Asic Design Verification Engineer Internship job openings:

Asic Design Verification Engineer Internship jobs near you

Principal FPGA/ASIC Verification Engineer (Onsite)

Prattwhitney

Fort Wayne, IN • On-site

$90 - $120/hr

Other

Posted 14 days ago

Job description

Position Overview

Principal Electrical or Computer Engineer – Onsite, FortWayne, IN (US‑Citizen required). Requires an active and transferable U.S. government‑issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of high‑performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.

Responsibilities
  • Verification environment architecture and design using SystemVerilog with OVM/UVM
  • Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group’s ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams, breaking down work, planning activities, and reporting status
Qualifications
  • Typically requires a STEM degree and minimum 8years of relevant experience, or an advanced degree and minimum 5years of experience
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment (at least 4years)
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience with chip‑level verification methodologies (constrained‑random testing, functional coverage analysis, assertion‑based verification)
  • Experience using revision control systems such as Git or Subversion
  • Demonstrated ability to work independently and mentor junior engineers
  • Preferred: Experience with ASIC/FPGA lab validation and debug, familiarity with DFT, manufacturability, and production test concepts, proficiency with Unix/Linux, scripting or software development
Security Clearance

U.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.

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