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Asic Design Verification Engineer Internship Jobs in Indiana

Principal FPGA Engineer

Wayne, IN ยท On-site

$123K - $150K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Principal FPGA Engineer

Fort Wayne, IN

$137K - $167K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...

Showing results 21-40

Asic Design Verification Engineer Internship information

What does an ASIC design verification engineer intern do?

An ASIC Design Verification Engineer Intern assists with testing and validating the functionality of Application-Specific Integrated Circuits (ASICs) during the hardware development process. Their responsibilities typically include writing test benches, developing verification environments, running simulations, and identifying bugs or design flaws before fabrication. Interns often use hardware description languages like Verilog or VHDL and verification methodologies such as UVM. This role is essential to ensure that the final ASIC design meets the required specifications and functions correctly.

What are the key skills and qualifications needed to thrive as an ASIC design verification engineer intern?

To thrive as an ASIC Design Verification Engineer Intern, you typically need a solid background in digital logic design, hardware description languages (HDLs) like Verilog or VHDL, and coursework in computer engineering or electrical engineering. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages like Python or Perl, and version control systems is highly valued. Strong analytical thinking, problem-solving abilities, and effective teamwork skills set exceptional candidates apart. These competencies are crucial for ensuring the functionality, reliability, and timely delivery of complex integrated circuits.

What are some typical challenges faced during an ASIC design verification engineer internship, and how can interns effectively address them?

Interns in ASIC design verification often encounter challenges such as understanding complex hardware specifications, learning new verification tools and methodologies, and debugging intricate design issues. To overcome these, it's important to proactively seek guidance from senior engineers, utilize available documentation and training resources, and actively participate in team meetings. Building strong communication skills and staying organized with test plans and bug tracking can also make the workflow smoother and more manageable.

What is the difference between Asic Design Verification Engineer Internship vs Asic Design Engineer?

AspectAsic Design Verification Engineer InternshipAsic Design Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's degree in Electrical Engineering or related field
Work EnvironmentInternship program, often in a corporate R&D or design teamFull-time professional role in ASIC design teams
ResponsibilitiesAssisting in verification testbenches, running simulations, learning verification toolsDesigning, implementing, and testing ASIC hardware components
DurationUsually 3-6 monthsFull-time ongoing role

The Asic Design Verification Engineer Internship is an entry-level, temporary position focused on assisting verification tasks, while the Asic Design Engineer role involves full responsibility for ASIC design and development. Internships provide hands-on experience, whereas full engineers lead projects and make design decisions.

What are popular job titles related to Asic Design Verification Engineer Internship jobs in Indiana?

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What cities in Indiana are hiring for Asic Design Verification Engineer Internship jobs?

Cities in Indiana with the most Asic Design Verification Engineer Internship job openings:

Full Time Raytheon 2026 - Multi-Product Power & Digital FPGA Engineer II

Prattwhitney

Fort Wayne, IN โ€ข On-site

$68.90 - $131.10/hr

Other

Medical, Dental, Vision, Life, Retirement, PTO

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Job description

FPGA Engineer II โ€“ Fort Wayne, IN

FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and effector products. Responsibilities include troubleshooting electronics in a lab or production environment, performing system and circuit level analysis, supporting failure investigations, maintaining and creating documentation, hardware and/or logic design, and interacting with multi-discipline groups including suppliers.

What You Will Do:
  • Work onsite at our Fort Wayne, IN location.
  • Provide full lifecycle support of production quality FPGA.
  • Generate FPGA designs.
  • Design and code in VHDL for reliability and maintainability.
  • Create complete documentation including requirements, verification plan, and user guides.
Basic Qualifications:
  • Master's degree in Electrical Engineering, Computer Engineering, or related STEM field.
  • Experience in FPGA/ASIC design (VHDL/Verilog) or verification (SystemVerilog).
  • Experience with AMD (Xilinx), Altera, or Microchip devices and tools such as AMD Vivado, Altera Quartus Prime Pro, or Libero.
  • Handsโ€‘on experience with integration and debugging of FPGA/ASIC in a lab environment.
  • Experience with source code management, design reviews, and code release in a team development environment.
  • U.S. citizenship required; ability to obtain and maintain a U.S. governmentโ€‘issued security clearance required.
We Prefer:
  • 3.0 cumulative GPA from an ABET accredited institution.
  • Demonstrated experience with VHDL or Verilog coding, simulation, and synthesis.
  • Knowledge of electrical circuit design, analysis, and troubleshooting using common lab equipment.
  • FPGA/ASIC design experience in embedded systems with ARM, Microblaze, or NIOS processors.
  • Experience with gigabit serial interfaces, multiโ€‘gigabit transceivers, constrained random verification in UVM, and highโ€‘level synthesis.
  • Experience with timing closure, clock domain crossing, reset domain crossing analysis, and constraint development.
  • Demonstrated ability to lead design efforts and/or small teams.
Salary & Benefits:
  • Salary range: $68,900 - $131,100 USD.
  • Benefits include medical, dental, vision, life insurance, shortโ€‘term disability, longโ€‘term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays.
  • Potential eligibility for annual shortโ€‘term and/or longโ€‘term incentive compensation programs.
EEO Statement:

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified individuals with a disability and protected veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veteransโ€™ Readjustment Assistance Act.

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