Junior Rtl Design Engineer Jobs in Indiana (NOW HIRING)

Professional Engineer (PE) * Sponsorship: Immigration related employment benefits, e.g. visa ... You'll design complex roadway projects while mentoring junior staff, coordinating with ...

This role will be responsible for managing engineering data, product structures, CAD integrations, and PLM workflows to ensure data accuracy and integrity throughout the product lifecycle. The ideal ...

Demonstrated ability to work independently and lead and/or mentor junior engineers within a team environment * Proven ability to design, implement, and execute verification testbenches for RTL blocks ...

Demonstrated ability to work independently and lead and/or mentor junior engineers within a team environment * Proven ability to design, implement, and execute verification testbenches for RTL blocks ...

Demonstrated ability to work independently and lead and/or mentor junior engineers within a team environment * Proven ability to design, implement, and execute verification testbenches for RTL blocks ...

... RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers

... RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers

... RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers

Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and ... Contribute to engineering estimates and technical planning efforts for new program pursuits * Plan ...

Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and ... Contribute to engineering estimates and technical planning efforts for new program pursuits * Plan ...

Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and ... Contribute to engineering estimates and technical planning efforts for new program pursuits * Plan ...

Our Roadway/Highway Design team is involved in a wide variety of street, roadway, highway and multi ... Mentor and coach junior and midlevel engineers, supporting their technical and professional ...

Mentor and provide technical guidance to junior engineering and CAD staff as appropriate. * Stay current with engineering principles, software advancements, and applicable codes and regulations.

Engage in knowledge transfer activities and mentorship of junior engineers. Qualifications You Must ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

Engage in knowledge transfer activities and mentorship of junior engineers. Qualifications You Must ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

Engage in knowledge transfer activities and mentorship of junior engineers. Qualifications You Must ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

Verification environment architecture and design usingSystemVerilogwith OVM/UVM * Creation of ... RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL ...

RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL ... Design for Test (DFT) and manufacturability issues * Experience with Unix, scripting, C/C++, and/or ...

RTL coding and simulation in VHDL or Verilog * Testbench development for the verification of RTL ... Design for Test (DFT) and manufacturability issues * Experience with Unix, scripting, C/C++, and/or ...

This role will also involve mentoring the development of junior engineers and designers. Duties ... Design change tooling or other required items for machine modifications. * Communicate design ...