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Junior Rtl Design Engineer Jobs in Gary, IN (NOW HIRING)

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $168K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

SWE Solutions

Design Engineer II

Chicago, IL · On-site

$38 - $51/hr

We are looking for an experienced Civil Design Engineer II to join our dynamic team and take a ... Oversee and review the work of junior engineers and designers to ensure accuracy and quality.

SWE Solutions

Design Engineer II

Chicago, IL · On-site

$38 - $51/hr

Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...

SWE Solutions

Design Engineer II

Chicago, IL · On-site

$38 - $51/hr

Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...

ADP, Inc.

Senior Design Engineer

Chicago Heights, IL · On-site

$80 - $100/hr

Define clear goals for all aspects of a project and develop steps for their proper execution. * Assist junior design engineers with their tasks, sharing best practices and techniques, and suggesting ...

New

Morgan Li, LLC

Senior Design Engineer

Chicago, IL · On-site

$100 - $125/hr

Define clear goals for all aspects of a project and develop steps for their proper execution. * Assist junior design engineers with their tasks, sharing best practices and techniques, and suggesting ...

New

Ashby

Design Engineer - Americas

Chicago, IL · Remote

$126K - $250K/yr

Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...

System One

Substation Design Engineer

Chicago, IL · Remote

$100K - $128K/yr

Substation Design Engineer Location: Chicago, IL Type: Direct Hire Contractor Work Model: Hybrid ... Provide technical guidance and informal mentorship to junior engineers where appropriate Required ...

System One

Substation Design Engineer

Chicago, IL · Remote

$100K - $128K/yr

Substation Design Engineer Location: Chicago, IL Type: Direct Hire Contractor Work Model: Hybrid ... Provide technical guidance and informal mentorship to junior engineers where appropriate Required ...

GFT.

Linear (Pipeline) Design Engineer

Chicago, IL

$75K - $150K/yr

Supervise and support the work of others and mentor junior level engineers & design/drafting technical staff. What you will bring to our firm: * Bachelor's Degree in Civil, Environmental, Mechanical ...

GFT.

Linear (Pipeline) Design Engineer

Chicago, IL · On-site

$75K - $150K/yr

Supervise and support the work of others and mentor junior level engineers & design/drafting technical staff. What you will bring to our firm: * Bachelor's Degree in Civil, Environmental, Mechanical ...

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All JobsRtl Design Engineer JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Gary, IN

Junior Rtl Design Engineer information

See Gary, IN salary details

$33.3K

$71.4K

$109K

How much do junior rtl design engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for junior rtl design engineer in Gary, IN is $71,447.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,300.00 and $79,600.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What cities near Gary, IN are hiring for Junior Rtl Design Engineer jobs?

Cities near Gary, IN with the most Junior Rtl Design Engineer job openings:

Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Gary, IN as of August 2026, with employment types broken down into 36% Full Time, and 64% Contract. Highlights an 100% In-person job distribution, with an average salary of $71,447 per year, or $34.3 per hour.

Junior FPGA Developer

Edgehog Trading

Chicago, IL • On-site

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 8 days ago

Key responsibilities

  • Design, implement, and verify RTL logic in Verilog or SystemVerilog for low-latency trading applications

  • Develop simulation testbenches and verification environments to validate FPGA designs before deployment

  • Participate in hardware bring-up, debugging, and optimize FPGA designs to meet timing constraints

Job description

About us
Edgehog Trading is a proprietary trading firm specializing in electronic options market making. We take a technology-driven approach, designing and operating automated, scalable systems to provide liquidity across markets.
Our team spans trading, engineering, and business operations, working together to build and support the systems that power the firm. We emphasize data-driven decision making, rigorous problem solving, and continuous improvement to navigate complex and evolving markets.
We operate in a highly collaborative environment where ideas can move quickly from concept to implementation, and where individuals are empowered to take ownership and contribute directly to the firm's growth.
What you'll do:
  • Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency trading applications
  • Develop simulation testbenches and functional verification environments to validate FPGA designs before hardware deployment
  • Work closely with senior FPGA engineers and the trading infrastructure team to understand latency requirements and translate them into hardware design decisions
  • Run synthesis, place-and-route, and static timing analysis; iterate on designs to meet strict timing constraints
  • Participate in hardware bring-up and on-board debugging, using waveform analysis and other diagnostic tools
  • Use AI tools to accelerate your development workflow - RTL review, testbench generation, debugging, and documentation
  • Grow your understanding of market data protocols (Ethernet, PCIe, exchange feed formats) as they relate to the systems you build

Qualifications and skills:
  • BS or MS in Electrical Engineering, Computer Engineering, or a related field
  • Hands-on experience with RTL design in Verilog or SystemVerilog - coursework, personal projects, or internship experience all count
  • Familiarity with FPGA simulation tools (e.g., ModelSim, QuestaSim, Vivado, Quartus) and the synthesis-to-deployment flow
  • Understanding of digital logic fundamentals: state machines, FIFOs, clock domain crossing, timing constraints
  • Comfort working in a Linux environment; Python, basic C or C++ is a plus
  • Ability and eagerness to incorporate AI tools into your development and debugging workflow
  • A strong desire to learn the HFT domain - no prior finance knowledge required
  • Strong analytical instincts: when something behaves unexpectedly in hardware, you dig until you find it

Why Edgehog:
  • Small team advantage: Direct access to founders and senior team members from day one
  • Ownership early: Manage real P&L and make meaningful impact within your first year
  • Cutting-edge tech: Work with our proprietary models and low-latency trading systems built in-house
  • Tight feedback loops: Monthly 1-on-1s with your mentor, quarterly reviews with leadership
  • Chicago-based: Affordable cost of living, vibrant trading community

Benefits:
  • Comprehensive health, dental, and vision insurance with premiums 100% covered by the firm
  • 401(k) with a 4% company match
  • Unlimited paid time off and sick leave
  • Free lunch, coffee, drinks, and snacks
  • Commuter benefits
  • Monthly happy hours and annual team events

The base salary range for this position is listed below. Base salary represents just one part of overall compensation; all full-time, permanent roles are eligible for a discretionary bonus and benefits, including items in the above list.
The base salary for this role is 100,000 - 175,000 USD per year

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