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Asic Verification Engineer Remote Jobs in Allen, TX

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ...

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.

IC Enable

AMS Verification Engineer

Richardson, TX · On-site +1

$122K/yr

Richardson, TX (Hybrid Schedule, Remote considered based on experience and qualifications) What You ... We specialize in advanced technology development, full-custom ASIC/SoC design, and electronics ...

IC Enable

RTL Design Engineer

Richardson, TX · On-site +1

$122K/yr

... ASIC/SoC development flows, and the ability to collaborate across design, verification, analog ... Richardson, TX (Hybrid, Remote considered based on experience and qualifications) What You'll Do:

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ...

Vital IT Services

Software Engineer (Remote)

Allen, TX · Remote

$95K - $115K/yr

Professional Core Experience: 3-6 years of verified full-stack or backend software engineering ... remote schedule based on team project needs rather than a rigid clock-in / in-office requirement.

Stryker

Salesforce Software Engineer (Remote)

Dallas, TX · On-site +1

$133K - $222K/yr

Remote As a Salesforce Software Engineer, you will play a key role in shaping how our U.S ... Coordinate QA and UAT testing activities to verify and validate new functionality before release.

Purple Hires Inc

Senior MBIST Engineer

Plano, TX · Remote

Senior MBIST Engineer Remote- Must be working as per PST time zone Rate- 70-75/hr on C2C Position ... Integrate and verify MBIST at the top level. * Develop, execute, and debug MBIST simulations using ...

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Asic Verification Engineer Remote information

See Allen, TX salary details

$81.9K

$145.2K

$192.5K

How much do asic verification engineer remote jobs pay per year?

As of Aug 25, 2026, the average yearly pay for asic verification engineer remote in Allen, TX is $145,179.00, according to ZipRecruiter salary data. Most workers in this role earn between $126,500.00 and $163,200.00 per year, depending on experience, location, and employer.

What does an ASIC Verification Engineer do?

An ASIC Verification Engineer is responsible for ensuring that an Application-Specific Integrated Circuit (ASIC) design functions as intended before it is manufactured. They develop and implement test plans, create verification environments using hardware description and verification languages like SystemVerilog or UVM, and run simulations to detect design flaws. Working remotely, these engineers collaborate with design teams using digital tools and communication platforms to review specifications, debug issues, and validate functionality. Their work is critical to reducing errors, saving costs, and ensuring high-quality chip production.

What are the key skills and qualifications needed to thrive as an ASIC Verification Engineer remote?

To thrive as an ASIC Verification Engineer (Remote), you need a solid background in digital design, verification methodologies, and hardware description languages such as Verilog or VHDL, often supported by a degree in electrical or computer engineering. Proficiency with simulation tools (e.g., Synopsys VCS, Cadence Xcelium), scripting languages (Python, Perl), and familiarity with UVM or SystemVerilog is typically required. Strong problem-solving skills, effective communication, and the ability to work independently and collaboratively in distributed teams are valuable soft skills. These competencies are crucial for ensuring robust chip validation, efficient remote collaboration, and successful project delivery in complex hardware development environments.

What are the main challenges of working remotely as an ASIC Verification Engineer, and how can they be addressed?

One of the main challenges of working remotely as an ASIC Verification Engineer is effective collaboration with design and verification teams, especially when debugging complex issues that benefit from real-time, face-to-face communication. Additionally, accessing hardware labs or simulation environments may require coordination with on-site colleagues. To address these challenges, it’s important to leverage video conferencing, screen sharing, and collaborative project management tools. Proactively communicating your progress and questions, and establishing regular check-ins with your team, can help ensure alignment and maintain productivity in a remote setup.

What is the difference between Asic Verification Engineer Remote vs Asic Design Engineer?

AspectAsic Verification Engineer RemoteAsic Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA/ASIC verification certificationsBachelor's/Master's in Electrical Engineering or Computer Engineering; VLSI design certifications
Work EnvironmentRemote, collaborative teams, virtual toolsTypically in-office or hybrid, design labs, CAD tools
Industry UsageCommon in semiconductor, electronics, and tech companies

While both roles require a strong background in VLSI and digital design, Asic Verification Engineers focus on testing and validating ASIC designs remotely, whereas Asic Design Engineers are involved in creating and designing ASICs, often working on-site. The roles share similar credentials but differ in daily tasks and work environment.

What are the most commonly searched types of Asic Verification Engineer jobs in Allen, TX?

The most popular types of Asic Verification Engineer jobs in Allen, TX are:

What are popular job titles related to Asic Verification Engineer Remote jobs in Allen, TX?

For Asic Verification Engineer Remote jobs in Allen, TX, the most frequently searched job titles are:

What job categories do people searching Asic Verification Engineer Remote jobs in Allen, TX look for?

The top searched job categories for Asic Verification Engineer Remote jobs in Allen, TX are:

What cities near Allen, TX are hiring for Asic Verification Engineer Remote jobs?

Cities near Allen, TX with the most Asic Verification Engineer Remote job openings:

Asic Verification Engineer Remote jobs near you
Infographic showing various Asic Verification Engineer Remote job openings in Allen, TX as of August 2026, with employment types broken down into 57% Full Time, and 43% Contract. Highlights an 100% Remote job distribution, with an average salary of $145,179 per year, or $69.8 per hour.

ASIC DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Re-posted 3 hours ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
Year of Exp: 8+ yrs to 15 yrs.
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.