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Uvm Verification Engineer Jobs (NOW HIRING)

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure.

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Uvm Verification Engineer information

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$80K

$142.6K

$203.5K

How much do uvm verification engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

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Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 92% Full Time, 3% Part Time, and 4% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, CA • On-site

The AES Group
See more jobs at The AES Groupexternal

$159K/yr

Contractor

Posted 13 days ago

Job description

Role: Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

Location: San Jose, CA

Let's create our future together at The AES Group!

About The AES Group

The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that make a positive impact. We help organizations modernize their technology through cloud, data, AI, engineering, cybersecurity, and emerging technologies.
Position Summary:

We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transcation Layer, Controller, PHY and Serdes. The candidate will be responsible for verification planning, methodology definition, UVM environment architecture, coverage closure, protocol compliance verification, and leadership of a team of verification engineers.
The ideal candidate should possess deep expertise in PCIe protocol, Transaction/Data Link/Physical Layers, LTSSM, PHY/SerDes interactions, UVM methodology, assertions, formal verification, emulation, and post-silicon debug support. The role requires close collaboration with Architecture, RTL Design, DFT, Firmware, Physical Design, and Validation teams.  
Key Responsibilities:
Verification Ownership
Own complete verification signoff for PCIe Gen5/Gen6 Controller and Subsystem.
Develop overall verification strategy and execution plan.
Drive verification activities from specification review through tape-out.
Review architecture, microarchitecture, and RTL specifications.
Define verification metrics and signoff criteria.
Create comprehensive verification plans covering:
Transaction Layer, Physical Layer, PIPE, and Data Link Layer
SR-IOV supporting large virtual functions.
Recovery Mechanisms
Map every protocol feature to:
Testcases, Assertion, Functional Coverage and Scoreboards.
Architect reusable UVM verification environments.
Build subsystem- and SoC-level verification environments.
Enable reuse from IP to subsystem to SoC verification.
Define coverage architecture.
Drive:
Functional Coverage
Code Coverage
Assertion Coverage
Cross Coverage
Analyze coverage holes and drive closure.
Establish signoff methodology and metrics.
Verify Controller-to-PHY integration.
Verify PIPE interface compliance.
Validate:
Equalization sequences
Link training
Recovery behavior
Speed changes
Lane width changes
Work closely with PHY and Analog teams.
 
Leadership Responsibilities:
Lead and mentor verification engineers.
Perform verification reviews and audits.
Drive schedule planning and execution tracking.
Interface with customers and program management.
Own verification signoff reviews.