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Uvm Verification Engineer Jobs (NOW HIRING)

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure.

Posted today

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Uvm Verification Engineer information

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$80K

$142.6K

$203.5K

How much do uvm verification engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

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Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

FPGA Verification Engineer - Santa Clara, CA/On-Site

STI

Santa Clara, CA • On-site

$159K - $195K/yr

Full-time

Re-posted 5 days ago

Job description

Title: FPGA Verification Engineer
Location: Santa Clara, CA/On-Site
Long Term
Mandatory Areas
Must Have Skills - FPGA Verification Engineer
Skill 1 - 8 + Years of in FPGA
Skill 2 - 5 +Years of Exp in UVM
Skill 2 - 5 +Years of Exp in System Verlilog
Good To have Skills
Skill 1 - Yrs of Exp -N/A
Skill 2 - Yrs of Exp -N/A
Skill 3 - Yrs of Exp -N/A
Skill 4 - Yrs of Exp -N/A
Mandatory if Applicable
Domain Experience (If any ) -N/A
Must have Certifications -N/A
Prior UST experience - Y / N
#NAME?
Job Description:
We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.
Key Responsibilities:
• Develop and execute comprehensive verification plans for FPGA designs.
• Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog).
• Write and debug test cases to verify functionality, performance, and corner cases.
• Perform code coverage and functional coverage analysis.
• Identify and debug issues, working closely with design engineers to resolve them.
• Document verification results and provide clear and concise reports.
• Participate in design reviews and contribute to the overall verification strategy.
• Stay up-to-date with the latest verification methodologies and tools.
Skills Required:
• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog and UVM verification methodology.
• Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
• Knowledge of code coverage and functional coverage analysis.
• Excellent debugging and problem-solving skills.
• Strong communication and collaboration skills.
Requirements
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in FPGA verification.
• Experience with scripting languages (e.g., Python, Perl).
• Familiarity with hardware description languages (e.g., VHDL, Verilog).

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