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Uvm Verification Engineer Jobs (NOW HIRING)

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Strong knowledge of System Verilog and UVM. Skilled in System C, C/C++, Python/perl. Highly ... verification. Understanding of prompt engineering and LLM workflow optimization.

Verification Engineer

Johns Creek, GA · Hybrid

$126K/yr

Role Overview We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Knowledge of System Verilog and UVM. Experience with System C, C/C++, Python/perl. Ability to ... verification. Understanding of prompt engineering and LLM workflow optimization.

About the Role As a Sr. Debug Design Verification Engineer, you will be responsible for Design for ... Create test case and testbench with UVM methodology; full chip/system functional verification, by ...

Design Engineer III

Sunnyvale, CA · On-site

$159K - $194K/yr

Design Engineer III Location: Sunnyvale, CA- Onsite Duration: Fulltime Experience: 10-15 Years ... Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers ...

Design Engineer III

Sunnyvale, CA · On-site

$161K - $197K/yr

Design Verification engineer for wearables silicon accelerator IPs - testbench development ... Minimum Qualifications Proven SystemVerilog + UVM verification experience (testbench architecture ...

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Uvm Verification Engineer information

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$80K

$142.6K

$203.5K

How much do uvm verification engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

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Infographic showing various Uvm Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 92% Full Time, 3% Part Time, and 4% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Staff Engineer, Design Verification Engineering

Chandler, AZ • On-site

Analog Devices
Electrical Equipment, Appliance, and Component Manufacturing • 5 - 10K employees

$150 - $200/hr

Other

Re-posted 7 days ago


Analog Devices rating

8.7

Company rating: 8.7 out of 10

Based on 19 frontline employees who took The Breakroom Quiz

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Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Job Title: Staff Engineer, Design Verification Engineering

Job Requisition: 1010.1197.6 / R262387

Job Location: Chandler, Arizona

Job Type: Full Time

Rate of Pay: $172,390 - $199,229 per year

Duties:

  • Define and verify interfaces, state machines, and controlling logic required to implement new products for Data Center, Energy, and Automotive applications.
  • Develop directed and constrained random test cases in SystemVerilog.
  • Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity.
  • SystemVerilog Assertion for Dynamic and Formal Verification.
  • Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models.
  • Product definition involvement.
  • Partial telecommute benefit (2 days/week work from home).

Requirements:

  • Must have a Master’s degree in Electrical Engineering, Materials Engineering, Physics, or closely related technical discipline (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing module level design performing with Verilog RTL and function verification.
  • Alternatively, employer will accept a Bachelor’s degree in Electrical Engineering, Materials Engineering, Physics, or closely related technical discipline (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing module level design performing with Verilog RTL and function verification.
  • Must also possess the following (quantitative experience requirements not applicable to this section):
  • Demonstrated Expertise (“DE”) with mixed signal IC verification techniques (SystemVerilog and UVM), verification test plan creation, coverage closure, test case and regression suite development.
  • DE defining, designing, and verifying experience with custom state machines and control logic for use with analog and mixed signal circuits such as data converters, linear regulators, high speed serial interfaces, and microcontrollers.
  • DE defining and implementing custom digital interfaces (I2C, SPI, and UART).
  • DE with logic synthesis with timing and placement constraints, timing and power analysis, logic equivalence checking, design for test, scan insertion, and ATPG.
  • DE with verification tools (Xcelium or VCS), and scripting languages (Perl, Python, and C).

Contact: Eligible for employee referral program.

Reference Position Number: R262387.

Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. Come join ADI – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare. ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

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About Analog Devices

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Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US