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Uvm Verification Engineer Jobs (NOW HIRING)

Altera

Senior Debug Verification Engineer

San Jose, CA

$149K - $215K/yr

About the Role As a Sr. Debug Design Verification Engineer , you will be responsible for Design for ... Create testcase and testbench with UVM methodology * Fullchip/system functional verification, by ...

FortifyIQ

Verification Engineer (Remote)

Salem, MA · Remote

$148K/yr

We're seeking a Verification Engineer to contribute to the validation of advanced chip designs ... You'll help create and maintain UVM environments, write tests, and ensure functional coverage for ...

Apple

Design Verification Engineer

Austin, TX

$120K - $210K/yr

Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and ... verification. Understanding of prompt engineering and LLM workflow optimization. Minimum ...

Apple

Design Verification Engineer

Austin, TX

$171K - $302K/yr

Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and ... verification. Understanding of prompt engineering and LLM workflow optimization. Minimum ...

Glow Networks

Principal Verification Engineer

Dallas, TX · On-site

$127K/yr

The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with ...

Apple

Design Verification Engineer

Austin, TX

$171K - $302K/yr

Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and ... verification. Understanding of prompt engineering and LLM workflow optimization. Minimum ...

Apple

Design Verification Engineer

Austin, TX

$120K - $210K/yr

Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and ... verification. Understanding of prompt engineering and LLM workflow optimization. Minimum ...

Apple

Design Verification Engineer

Austin, TX

$171K - $302K/yr

Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and ... verification. Understanding of prompt engineering and LLM workflow optimization. Minimum ...

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Uvm Verification Engineer information

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$80K

$142.6K

$203.5K

How much do uvm verification engineer jobs pay per year?

As of Jul 1, 2026, the average yearly pay for uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM Verification Engineer job?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the key skills and qualifications needed to thrive in the Uvm Verification Engineer position, and why are they important?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

What are some typical responsibilities of a Uvm Verification Engineer on a daily basis?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

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Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 22% Full Time, 61% Part Time, and 17% Nights. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
SoC Verification Engineer - NoC / UVM

SoC Verification Engineer - NoC / UVM

Advanced Micro Devices, Inc

San Jose, CA • On-site

$145K/yr

Full-time

Posted 21 days ago

Advanced Micro Devices rating

8.4

Company rating: 8.4 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

22nd of 141 rated electronics manufacturers

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
The verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.
THE PERSON:
You are a skilled verification engineer with strong expertise in System Verilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.
KEY RESPONSIBILITIES:
  • Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
  • Interact with architects and design engineers to create a comprehensive verification test plan
  • Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality improvements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE:
  • Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
  • Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Experience in block level NOC (Net work on Chip) verification is a plus.
  • Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
  • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.

ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

This role is not eligible for visa sponsorship.
#LI-EV1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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