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Uvm Verification Engineer Jobs (NOW HIRING)

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

TRC Talent Solutions

Verification Engineer

Suwanee, GA · Hybrid

$126K/yr

Role Overview We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power ...

Draper

UVM Digital Verification Engineer

Cambridge, MA · On-site

$75K - $156K/yr

Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Strong knowledge of System Verilog and UVM. Skilled in System C, C/C++, Python/perl. Highly ... verification. Understanding of prompt engineering and LLM workflow optimization.

Advanced Micro Devices

$150 - $190/hr

Design testbenches in System Verilog and UVM to complete verification of the design in an efficient ... Debug tests with design engineers to deliver functionally correct design blocks and close the ...

New

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Knowledge of System Verilog and UVM. Experience with System C, C/C++, Python/perl. Ability to ... verification. Understanding of prompt engineering and LLM workflow optimization.

Siri InfoSolutions Inc

Design Engineer III

Sunnyvale, CA · On-site

$159K - $194K/yr

Design Engineer III Location: Sunnyvale, CA- Onsite Duration: Fulltime Experience: 10-15 Years ... Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers ...

Altera

Senior Debug Verification Engineer

San Jose, CA · On-site

$149.10 - $215/hr

About the Role As a Sr. Debug Design Verification Engineer, you will be responsible for Design for ... Create test case and testbench with UVM methodology; full chip/system functional verification, by ...

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Uvm Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do uvm verification engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

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Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

UVM Digital Verification Engineer

Draper

Cambridge, MA • On-site

$75K - $156K/yr

Full-time

Re-posted 4 days ago

Job description

Overview:
Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.
Job Description Summary:
Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.
Job Description:
Duties/Responsibilities
  • Design and simulate circuits at transistor-level to implement architecture and requirement specifications
  • Contribute to system-level design
  • Optimize hardware designs for performance, power, and cost
  • Evaluate the hardware feasibility of complex algorithms and requirements
  • Contribute to complex chip architectures and designs
  • Contribute to efforts to drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements
  • Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics.
  • Perform other duties as assigned

Skills/Abilities
  • Proficiency in integrated circuit design
  • Understanding of integrated circuits, semiconductors, and general computer architecture
  • Ability to write detailed design specifications
  • Excellent verbal and written communication skills
  • Excellent mathematical skills
  • Excellent organizational skills and attention to detail
  • Excellent time management skills with the proven ability to meet deadlines
  • Strong analytical and problem-solving skills
  • Ability to prioritize tasks
  • Demonstrate strong organization, planning, and time management skills to achieve program goals

Education
Requires a bachelor's degree in Engineering, or related field. Masters degree preferred.
Experience
Requires 3-5 years of experience with a bachelor's degree, or 0-2 years of experience with a master's degree in Integrated Circuits or ASIC Hardware Engineering or related.
Additional Job Description:
You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.
  • Develop verification and test plans
  • Develop UVM Agents for proprietary buses
  • Instantiate VIPs for industry standard buses
  • Work in both block-level/chip-level UVM testbench environment
  • Work with RTL designers to resolve simulation issues
  • Implement cover groups according to design requirements
  • Work on code and functional coverage closures to achieve 100%
  • Perform code reviews and to mentor junior engineers in the group
  • Fluent in System Verilog including SVA
  • Recent experience with UVM/UVMF
  • Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
  • Familiarity with at least one IEEE bus standard. Experience with DDR3/DDR4, Amba Axi protocols
  • Firm grasp of constrained-random testing and coverage-driven verification
  • Experience with formal analysis
  • Practice using Python, Perl, Bash or other scripting languages
  • Ability to work in a Linux environment
  • Strong analysis and problem-solving skills

Applicants selected for this position will be required to obtain and maintain a government security clearance.
Connect With Draper for Future Opportunities! If you don't find the right posting in our Career Opportunities, you may submit your resume for future consideration.
Job Location - City:
Cambridge
Job Location - State:
Massachusetts
Job Location - Postal Code:
02139-3563
The US base salary range for this full-time position is
$75,000.00 - $156,000.00
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Union ranges will be in compliance with the collective bargaining agreement's approved rates by location and role. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and does not include bonuses or benefits.
Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. If this specific job opportunity and the chance to work at a nationally renowned R&D innovation company appeals to you, apply now www.draper.com/careers.
Draper is committed to creating an inclusive environment. We understand the value of inclusivity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, national origin, veteran status, or genetic information. Draper is committed to providing access, equal opportunity, and reasonable accommodation for individuals with disabilities in employment, its services, programs, and activities. To request reasonable accommodation, please contact hr@draper.com.

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