SoC Design and Verification
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating. * At least 1-year experience in any of the Scripting: Perl, Tcl, python. * Experience with low power design. * Must ...
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating. * At least 1-year experience in any of the Scripting: Perl, Tcl, python. * Experience with low power design. * Must ...
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating. * At least 1-year experience in any of the Scripting: Perl, Tcl, python. * Experience with low power design. * Must ...
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 3 years relevant industry experience.
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 3 years relevant industry experience.
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 10 years relevant industry experience.
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 10 years relevant industry experience.
Beaverton, OR · On-site
Use Verilog to design and System Verilog for block level verification * Assist the Verification team in reviewing and debugging test cases * Run LINT and CDC checks on the RTL code and fix ...
Beaverton, OR · On-site
Use Verilog to design and System Verilog for block level verification * Assist the Verification team in reviewing and debugging test cases * Run LINT and CDC checks on the RTL code and fix ...
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating * At least 1 year experience in any of the Scripting: Perl, Tcl, python * Experience with low power design * Must have ...
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating * At least 1 year experience in any of the Scripting: Perl, Tcl, python * Experience with low power design * Must have ...
Hillsboro, OR · On-site
$164K - $311K/yr
Proficiency with C/C++, System Verilog coding and debug. * Knowledge and experience with x86 or any other computer architectures. * Familiarity with version control software (GIT). * Experience with ...
Hillsboro, OR · On-site
$164K - $311K/yr
Proficiency with C/C++, System Verilog coding and debug. * Knowledge and experience with x86 or any other computer architectures. * Familiarity with version control software (GIT). * Experience with ...
Hillsboro, OR · On-site
$108K - $201K/yr
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Hillsboro, OR · On-site
$108K - $201K/yr
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Hillsboro, OR · Hybrid
$108K - $201K/yr
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Hillsboro, OR · Hybrid
$108K - $201K/yr
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
Hillsboro, OR · Hybrid
$108K - $201K/yr
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Hillsboro, OR · Hybrid
$108K - $201K/yr
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Hillsboro, OR · Hybrid
$111K - $147K/yr
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 7+ years of experience with RTL Design * Good English skills ...
Hillsboro, OR · Hybrid
$111K - $147K/yr
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 7+ years of experience with RTL Design * Good English skills ...
$121K - $174K/yr
DE verifying integration and functionality of design utilizing verification tools and techniques, including Verilog, System Verilog, and overall ASIC design flow. * DE working with verification plan ...
$121K - $174K/yr
DE verifying integration and functionality of design utilizing verification tools and techniques, including Verilog, System Verilog, and overall ASIC design flow. * DE working with verification plan ...
Beaverton, OR · On-site
$121K - $174K/yr
DE verifying integration and functionality of design utilizing verification tools and techniques, including Verilog, System Verilog, and overall ASIC design flow. * DE working with verification plan ...
Beaverton, OR · On-site
$121K - $174K/yr
DE verifying integration and functionality of design utilizing verification tools and techniques, including Verilog, System Verilog, and overall ASIC design flow. * DE working with verification plan ...
OR · Hybrid
This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools. * Partnering closely with our clocks architecture and design team to validate our clocks design.
Tualatin, OR · On-site
$154K - $247K/yr
Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification * Expertise with UVM testbench development and Verification IP integration
Tualatin, OR · On-site
$154K - $247K/yr
Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification * Expertise with UVM testbench development and Verification IP integration
Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification * Expertise with UVM testbench development and Verification IP integration
Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification * Expertise with UVM testbench development and Verification IP integration
$141K - $200K/yr
Writing System Verilog Assertions (SVA) Preferred Qualifications: Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
$141K - $200K/yr
Writing System Verilog Assertions (SVA) Preferred Qualifications: Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
OR · Remote
$200K - $300K/yr
Experience with Verilog/System Verilog , UVM, Python, TCL, C/C++ * Experience with the full verification flow , from spec to coverage analysis to gate level sim * Debugging failures in simulation to ...
OR · Remote
$200K - $300K/yr
Experience with Verilog/System Verilog , UVM, Python, TCL, C/C++ * Experience with the full verification flow , from spec to coverage analysis to gate level sim * Debugging failures in simulation to ...
$56.6K - $67.5K
2% of jobs
$67.5K - $78.4K
4% of jobs
$78.4K - $89.3K
7% of jobs
$89.3K - $100.2K
9% of jobs
$103.2K is the 25th percentile. Wages below this are outliers.
$100.2K - $111.1K
10% of jobs
$111.1K - $122K
7% of jobs
$122K - $132.9K
10% of jobs
The median wage is $134.7K / yr.
$132.9K - $143.8K
6% of jobs
$143.8K - $154.7K
3% of jobs
$165.3K is the 75th percentile. Wages above this are outliers.
$154.7K - $165.7K
17% of jobs
$165.7K - $176.6K
24% of jobs
$56.6K
$134.5K
$176.6K
SystemVerilog Engineers typically spend their days writing, debugging, and optimizing verification testbenches and scripts to ensure hardware designs function as intended. They often collaborate closely with design engineers, participating in design reviews, and providing feedback on specification documents. Frequent interactions with verification teams help in developing comprehensive test plans and resolving functional issues. The role requires proactive communication and teamwork, as successful verification projects depend on close cooperation between multiple engineering disciplines.
To thrive as a SystemVerilog Engineer, you should have a solid background in digital design, logic verification, and a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys VCS, Cadence Incisive, and UVM methodology is often required, along with relevant certifications or hands-on project experience. Strong analytical thinking, problem-solving, and effective communication are crucial soft skills for collaborating with design and verification teams. Mastery of these skills ensures robust and efficient verification processes, which are critical for delivering high-quality hardware designs on schedule.
A SystemVerilog job typically involves designing, verifying, and testing digital hardware using the SystemVerilog language. Engineers in this role work on developing testbenches, writing assertions, and simulating circuits to ensure functional correctness. These jobs are common in semiconductor and ASIC/FPGA design industries, where verification engineers use SystemVerilog with methodologies like UVM. Strong knowledge of RTL design, verification methodologies, and debugging tools is essential.

SonSoft Inc. is a USA based corporation duly organized under the laws of the Commonwealth of Georgia. SonSoft Inc is growing at a steady pace specializing in the fields of Software Development, Software Consultancy, and Information Technology Enabled Services.
** U.S. Citizens and those who are authorized to work independently in the United States are encouraged to apply. We are unable to sponsor at this time.
Note:-
** All your information will be kept confidential according to EEO guidelines.
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Sonsoft , Inc. is a USA based corporation duly organized under the laws of the Commonwealth of Georgia. Sonsoft Inc. is growing at a steady pace specializing in the fields of Software Development, Software Consultancy and Information Technology Enabled Services.
It services
51 - 200 Employees
Alpharetta, GA, US
2007