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Asic Design Verification Engineer Internship Jobs in Oregon

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

K2 Space

Senior ASIC Design Verification Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Use Verilog to design and System Verilog for block level verification * Assist the Verification ...

Nvidia

Senior ASIC Verification Engineer

Hillsboro, OR · On-site

NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... As a senior member of our verification team, you'll understand the design & implementation with ...

Nvidia

Senior ASIC Verification Engineer

OR · On-site +1

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive ... The complexity of the clocks and resets design has increased many folds. This requires ...

Apple

ASIC Design Engineer

Beaverton, OR · On-site

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ...

Apple

ASIC Design Engineer

Beaverton, OR

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$184K - $324K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$184K - $324K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$129K - $194K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

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Asic Design Verification Engineer Internship information

What does an ASIC design verification engineer intern do?

An ASIC Design Verification Engineer Intern assists with testing and validating the functionality of Application-Specific Integrated Circuits (ASICs) during the hardware development process. Their responsibilities typically include writing test benches, developing verification environments, running simulations, and identifying bugs or design flaws before fabrication. Interns often use hardware description languages like Verilog or VHDL and verification methodologies such as UVM. This role is essential to ensure that the final ASIC design meets the required specifications and functions correctly.

What are the key skills and qualifications needed to thrive as an ASIC design verification engineer intern?

To thrive as an ASIC Design Verification Engineer Intern, you typically need a solid background in digital logic design, hardware description languages (HDLs) like Verilog or VHDL, and coursework in computer engineering or electrical engineering. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages like Python or Perl, and version control systems is highly valued. Strong analytical thinking, problem-solving abilities, and effective teamwork skills set exceptional candidates apart. These competencies are crucial for ensuring the functionality, reliability, and timely delivery of complex integrated circuits.

What are some typical challenges faced during an ASIC design verification engineer internship, and how can interns effectively address them?

Interns in ASIC design verification often encounter challenges such as understanding complex hardware specifications, learning new verification tools and methodologies, and debugging intricate design issues. To overcome these, it's important to proactively seek guidance from senior engineers, utilize available documentation and training resources, and actively participate in team meetings. Building strong communication skills and staying organized with test plans and bug tracking can also make the workflow smoother and more manageable.

What is the difference between Asic Design Verification Engineer Internship vs Asic Design Engineer?

AspectAsic Design Verification Engineer InternshipAsic Design Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's degree in Electrical Engineering or related field
Work EnvironmentInternship program, often in a corporate R&D or design teamFull-time professional role in ASIC design teams
ResponsibilitiesAssisting in verification testbenches, running simulations, learning verification toolsDesigning, implementing, and testing ASIC hardware components
DurationUsually 3-6 monthsFull-time ongoing role

The Asic Design Verification Engineer Internship is an entry-level, temporary position focused on assisting verification tasks, while the Asic Design Engineer role involves full responsibility for ASIC design and development. Internships provide hands-on experience, whereas full engineers lead projects and make design decisions.

What are popular job titles related to Asic Design Verification Engineer Internship jobs in Oregon?

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Asic Design Verification Engineer Internship jobs near you

Principal ASIC Design Verification Engineer

K2 Space

OR • On-site, Remote

$190K - $285K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 23 days ago

Job description

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Drive advancement of DV methodologies and improvements.
  • Manage external IP providers and verification partners when needed.
  • Take lead on large and/or complex systems. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
  • Experience with developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
  • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
  • Involvement in post-silicon validation planning and execution. 

Nice to Have

  • Experience with low power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $285,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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