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Physical Design Jobs in Oregon (NOW HIRING)

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Beaverton, OR

$141K - $145K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

CPU Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

CPU Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

Physical Design Engineer

Hillsboro, OR · On-site

$148K - $152K/yr

Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will be developing and supporting mixed signal and custom digital hard IPs. The job will entail: files ...

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

As a Qubit Control Physical Design Engineer, you will drive or participate in the following: Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious ...

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

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Physical Design information

See Oregon salary details

$100.4K

$149.6K

How much do physical design jobs pay per year?

As of Aug 14, 2026, the average yearly pay for physical design in Oregon is $147,395.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $148,000.00 per year, depending on experience, location, and employer.

What is physical design in the context of electronics and semiconductors?

Physical design refers to the process of transforming a circuit's logical representation into a geometrical layout that can be manufactured on a semiconductor chip. This involves placing and routing the various components, such as transistors and interconnections, while meeting performance, power, and area constraints. Physical design engineers use specialized software tools to optimize the layout and ensure it adheres to manufacturing rules. The process is a critical step in the development of integrated circuits (ICs) and directly impacts the chip’s speed, power consumption, and size.

What are the key skills and qualifications needed to thrive as a physical design engineer, and why are they important?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, digital circuit design, and VLSI concepts, usually supported by a relevant degree. Proficiency with EDA tools like Cadence, Synopsys, or Mentor Graphics, as well as familiarity with scripting languages (e.g., TCL, Perl), is essential. Strong problem-solving, attention to detail, and effective communication skills help you address complex design challenges and collaborate within cross-functional teams. These competencies are crucial for optimizing chip layouts, ensuring manufacturability, and meeting performance and timing requirements in semiconductor development.

What are some common challenges faced by physical design engineers in meeting timing closure during chip development?

Physical Design engineers often encounter challenges in achieving timing closure due to factors such as increasing circuit complexity, tight power and area constraints, and process variations. Meeting timing goals requires careful floorplanning, placement, and routing, as well as close collaboration with logic design and verification teams to resolve critical path issues. Engineers must also frequently iterate designs and use advanced EDA tools to optimize performance while balancing trade-offs between speed, power, and manufacturability.

How to get into physical design?

To enter physical design, candidates typically need a bachelor's degree in electrical engineering, computer engineering, or a related field. Gaining experience with hardware description languages like VHDL or Verilog, and proficiency in EDA tools such as Synopsys or Cadence, is essential. Internships or entry-level positions in chip design can also provide valuable practical experience.

What is the difference between Physical Design vs Logic Design?

AspectPhysical DesignLogic Design
Primary FocusTranslating logical circuits into physical layoutsCreating logical circuit schematics and functional specifications
Skills RequiredEDA tools, layout constraints, circuit optimizationHardware description languages, digital logic, circuit theory
Work EnvironmentASIC/FPGA design teams, semiconductor companiesDesign teams, electronic design automation (EDA) environments
CertificationsTypically none specific, but EDA tool proficiency is valuedHardware description language certifications (e.g., VHDL, Verilog)

Physical Design and Logic Design are closely related stages in chip development. Logic Design focuses on creating the logical circuit functions, while Physical Design involves implementing those functions into physical layouts on silicon. Both roles require knowledge of digital circuits, but Physical Design emphasizes layout optimization and tool proficiency, whereas Logic Design centers on circuit behavior and description.

What cities in Oregon are hiring for Physical Design jobs?

Cities in Oregon with the most Physical Design job openings:

Infographic showing various Physical Design job openings in Oregon as of August 2026, with employment types broken down into 78% Full Time, and 22% Part Time. Highlights an 100% In-person job distribution, with an average salary of $147,395 per year, or $70.9 per hour.

Physical Design Engineer

Apple

Beaverton, OR • On-site

$141K - $145K/yr

Full-time

Re-posted 25 days ago


Apple rating

8.0

Company rating: 8.0 out of 10

Based on 677 frontline employees who took The Breakroom Quiz

7th of 30 rated technology retailers


Job description

At Apple we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing, and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design.
Description
As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.
Minimum Qualifications
Bachelors of Science in Electrical Engineering and 10+ years experience preferred.
Preferred Qualifications
Deep design experience in high PHY and/or SOC designs.
Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route.
Experience in developing and implementing Power-grid and Clock specifications.
Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools.
Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools.
Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

What Apple employees say

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Benefits

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Get the full story on Breakroom


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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976