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Work From Home Physical Design Engineer Jobs in Oregon

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working ... Work with external physical design service providers and internal leads to review deliverables ...

... ranging from consumer graphics to self-driving cars and the growing field of artificial ... will work closely with fellow design engineers, architects, verification engineers, and physical ...

We are excited to announce that currently we are looking for a 100% remote (work from home-WFH) contract Pharmacy Support Call Center Representative to join our team. In this position, you will ...

WORK FROM HOME

Lake Oswego, OR · On-site +1

$300 - $500/wk

We are looking for individuals interested in working from home, remotely, as life insurance sales representatives. We are hiring coachable individuals comfortable with a 100% commission based income ...

You'll work directly with interposer design engineers, package architects, and foundry partners to ... Ways to stand out from the crowd: Good understanding of VLSI package design along with interposer ...

... ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing ... If so, we want to hear from you. Your base salary will be determined based on your location ...

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

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Work From Home Physical Design Engineer information

What is a work from home physical design engineer?

A Work From Home Physical Design Engineer is responsible for the back-end design and implementation of integrated circuits (ICs) while working remotely. They handle tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure to ensure chip performance and manufacturability. These engineers collaborate with other teams, including RTL designers and verification engineers, using electronic design automation (EDA) tools. Strong knowledge of physical design methodologies, semiconductor technology, and scripting is essential for success in this role.

What are the key skills and qualifications needed to thrive as a work from home physical design engineer?

To thrive as a Work From Home Physical Design Engineer, you need a strong background in digital and analog circuit design, ASIC/FPGA implementation, and a degree in Electrical or Computer Engineering. Mastery of industry-standard EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as familiarity with scripting languages and relevant certifications like Design Verification, is often required. Excellent time management, proactive communication, and problem-solving abilities are crucial soft skills when working remotely within distributed teams. Together, these skills ensure the engineer can independently deliver high-quality designs while effectively collaborating with cross-functional teams in a virtual environment.

What are some common challenges faced by work from home physical design engineers, and how can they be addressed?

Work From Home Physical Design Engineers often encounter challenges such as coordinating design iterations with global teams, maintaining version control remotely, and ensuring timely communication despite different time zones. To address these challenges, it's important to be proactive in scheduling regular virtual meetings, effectively use collaborative platforms for project tracking and documentation, and participate in code/design reviews online. Many companies also encourage a strong onboarding process and provide access to remote IT support for EDA tool setups to ensure seamless workflow. Staying disciplined with self-management and scheduling helps maintain productivity and meet project deadlines when working independently. Embracing these strategies allows remote engineers to stay engaged and work effectively alongside their on-site counterparts.

What job categories do people searching Work From Home Physical Design Engineer jobs in Oregon look for?

The top searched job categories for Work From Home Physical Design Engineer jobs in Oregon are:

What cities in Oregon are hiring for Work From Home Physical Design Engineer jobs?

Cities in Oregon with the most Work From Home Physical Design Engineer job openings:

Infographic showing various Work From Home Physical Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 1% As Needed, 66% Full Time, 30% Part Time, and 3% Contract. Highlights an 91% Physical, 1% Hybrid, and 8% Remote job distribution.

Principal ASIC Physical Design Engineer

K2 Space

OR • On-site, Remote

$190K - $280K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 10 days ago


Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022