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Tapeout Design Engineer Jobs (NOW HIRING)

Talent 101, Inc.

Physical Design Engineer

Frisco, TX · On-site

$127K - $131K/yr

About Talent 101 Inc Talent 101 is an Engineering and IT services provider, with clients that range ... Deliver signoff reports and support final tapeout package creation * 5+ years' Physical Design ...

Talent 101 Inc

Physical Design Engineer

Frisco, TX · On-site

$127K - $131K/yr

About the role This is a full time position with our company doing Physical Design Engineering ... Deliver signoff reports and support final tapeout package creation Qualifications * 5+ years ...

Qualcomm

Physical Design Engineer- Senior

Austin, TX · On-site

$115K - $173K/yr

As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using ... This role requires strong expertise in physical design flow, tapeout readiness, and Power ...

SambaNova

Senior Hardware Design Engineer

Austin, TX · On-site

A block stays with the engineer who wrote it through PPA closure, tapeout, and bring-up, so you debug your own design in silicon. About the role SambaNova Senior Hardware Design Engineers design ...

Ralliant

ASIC Physical Design Engineer

Boulder, CO · On-site

$143K - $147K/yr

ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This ... tapeout-ready design. * Develop and maintain scripts, flows, documentation, and review materials ...

Jobtailor

Silicon Design Engineer

San Jose, CA · On-site

Demonstrated success taking designs from synthesis through tapeout on real silicon * Proficiency in ... Electrical Engineering * Computer Engineering * Design Verification * Quality Checks * Tapeout ...

Ralliant

ASIC Physical Design Engineer

Boulder, CO · On-site

$141K - $145K/yr

... tapeout-ready design. • Develop and maintain scripts, flows, documentation, and review materials that improve physical design methodology, automation, quality, and schedule predictability. Minimum ...

SolGenie

ASIC Physical Design Engineer

Lafayette, IN · On-site

$130K - $134K/yr

Tapeout , Signoff , DRC/LVS/PEX, Customer interaction Job Responsibilities: * Act as the primary ... Collaborate with internal design, layout, and engineering teams to ensure manufacturability

Ricursive

Chip Design Engineer

Palo Alto, CA · On-site

ABOUT THE ROLE Physical design is where AI-driven chip design gets graded: every placement, clock ... tapeout, and who has personally fought complex blocks to closure at an advanced node. Your ...

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All JobsTapeout Design Engineer Jobs

Tapeout Design Engineer information

See salary details

$40.5K

$88.2K

$158.5K

How much do tapeout design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for tapeout design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is a tapeout design engineer?

Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.

What are the key skills and qualifications needed to thrive as a tapeout design engineer?

To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.

What are some common challenges tapeout design engineers face during the tapeout process, and how can they be addressed?

Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.

What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?

AspectTapeout Design EngineerASIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering or related field; strong digital design skills
Work EnvironmentSemiconductor companies, chip design firms, EDA tool providersSemiconductor companies, integrated circuit design firms
Industry UsageFocuses on final chip layout and manufacturing readinessDesigns the digital architecture and logic of chips

While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.

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Tapeout Design Engineer jobs near you
Infographic showing various Tapeout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Physical Design Engineer

Frisco, TX • On-site

Talent 101, Inc.
Business Management Consulting • 51 - 200 employees
Learn more about Talent 101, Inc.external

$127K - $131K/yr

Full-time

Re-posted 27 days ago

Job description

About Talent 101 Inc
Talent 101 is an Engineering and IT services provider, with clients that range from start-up to Fortune 500. We specialize in solutions for the Semiconductor, Automotive, Electronics, Energy, Telecom, and Defense industries.
About the role
  • This is a full time position with our company doing Physical Design Engineering.

What you'll do
  • Lead end to end Physical Design from floorplan to GDS
  • Own full PnR flow: placement, CTS, routing, optimization, ECOs
  • Run, debug, and close DRC/LVS for foundry clean signoff
  • Drive timing closure using Tempus with strong constraint ownership
  • Perform synthesis and QoR optimization using Genus
  • Improve PPA across block level and IP level designs
  • Partner with internal IP teams to prepare blocks for tapeout readiness
  • Deliver signoff reports and support final tapeout package creation
  • 5+ years' Physical Design experience
  • Strong hands on proficiency with Cadence Innovus, Tempus, and Genus
  • Proven success supporting internal IP tapeout
  • Ability to collaborate across RTL, verification, and integration teams

Talent101 pays referral fees.
Applicants must be at least 18 years or older, must be willing to take a drug test and background check as part of the selection process and must have legal authorization to work in the United States.
Talent 101 is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to protected characteristics, including race, color, religion, sex, national origin, disability, veteran status, sexual orientation, gender identity or age.

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