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Tapeout Design Engineer Jobs (NOW HIRING)

onsemi

Design Engineer

Scottsdale, AZ · On-site

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.

Onsemi

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.

Onsemi

Design Engineer

Scottsdale, AZ · On-site

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.

onsemi

Design Engineer

Scottsdale, AZ · On-site

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.

Lumilens

Sr. Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry‑standard ... Engineering, or a related field. * Experience: 8+ years of hands‑on physical design experience ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Will work of full project lifecycle from inception to tapeout. Qualifications: * BSEE with 5+ years ...

Lumilens

Sr. Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard ... Engineering, or a related field. * Experience: 8+ years of hands-on physical design experience ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Will work of full project lifecycle from inception to tapeout. Qualifications: * BSEE with 5+ years ...

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA · On-site

$120K - $171K/yr

High-Speed Analog EDA/CAD Engineer: Brief Description: Full-time position. Infinera is seeking an ... Execute and support layout efforts including archive and tapeout processes Minimum Expertise ...

Tenstorrent

Physical Design Engineer, PnR

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions ... You'll own the complete implementation flow from synthesis to tapeout, working alongside world ...

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All JobsTapeout Design Engineer Jobs

Tapeout Design Engineer information

See salary details

$40.5K

$88.2K

$158.5K

How much do tapeout design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for tapeout design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is a tapeout design engineer?

Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.

What are the key skills and qualifications needed to thrive as a tapeout design engineer?

To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.

What are some common challenges tapeout design engineers face during the tapeout process, and how can they be addressed?

Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.

What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?

AspectTapeout Design EngineerASIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering or related field; strong digital design skills
Work EnvironmentSemiconductor companies, chip design firms, EDA tool providersSemiconductor companies, integrated circuit design firms
Industry UsageFocuses on final chip layout and manufacturing readinessDesigns the digital architecture and logic of chips

While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.

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What cities are hiring for Tapeout Design Engineer jobs?

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What states have the most Tapeout Design Engineer jobs?

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What are popular job titles related to Tapeout Design Engineer jobs?

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Tapeout Design Engineer jobs near you
Infographic showing various Tapeout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Design Engineer

Scottsdale, AZ • On-site

onsemi
Electrical Equipment, Appliance, and Component Manufacturing • 10K+ employees
Learn more about onsemiexternal

Full-time

Re-posted 11 days ago

Onsemi rating

8.2

Company rating: 8.2 out of 10

Based on 21 frontline employees who took The Breakroom Quiz

Job description

An exciting opportunity to join a high growth business unit with expertise in device physics to support development of small signal and protection devices for industrial, automotive and wireless applications.

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to interact with cross-functional team of engineers in Design, Application, Corporate R&D, Foundry, Product and Marketing to develop and release-to-market industry-leading analog protection and small signal products.

onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world's most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here:

https://www.onsemi.com/careers/career-benefits

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.


onsemi is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws.

If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.
  • Master or higher in Electrical Engineering or related field with emphasis on semiconductor device physics and process fabrication
  • Must have experience with Cadence environment for simulation tools
  • Prefer experience with 3D EM simulation and/or analog/RF circuit analysis tools is a plus
  • A track record of innovation and publications is a plus
  • Must have good communication skills and work ethic
  • A track record of leadership skills and the ability to work with minimal supervision
  • Strong skills in device physics and TCAD simulations to define new device structures for ESD protection.
  • Design, layout and verification of protection and small signal products to meet the specifications with device and circuit analysis tools
  • Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.
  • Drive high quality and thorough design reviews including a playback to device targets.
  • Collaborate with marketing, product engineering and project managers to surmount challenges and maintain development schedules
  • Take joint responsibility for product-manufacturability and yield
  • Participate in roadmap and strategy development.
  • Excellent interpersonal and presentation skills. Possess initiative and motivation to work with cross-functional teams effectively.

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