SoC Physical Design Engineer, STA/Timing
$141.50K - $145.70K/yr
... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ... design STA and/or Timing Closure. Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$141.50K - $145.70K/yr
... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ... design STA and/or Timing Closure. Programming skills with Perl and TCL.
Physical Design Engineer (7452)
San Jose, CA · On-site
$155.70K - $160.30K/yr
You will be instrumental in the physical implementation and tapeout of complex test vehicles ... design cycle. Minimum Qualifications * Master's Degree or higher in Electrical Engineering or ...
Physical Design Engineer (7452)
San Jose, CA · On-site
$155.70K - $160.30K/yr
You will be instrumental in the physical implementation and tapeout of complex test vehicles ... design cycle. Minimum Qualifications * Master's Degree or higher in Electrical Engineering or ...
Physical Design Engineer (7452)
San Jose, CA · On-site
$155.70K - $160.30K/yr
You will be instrumental in the physical implementation and tapeout of complex test vehicles ... design cycle. Minimum Qualifications * Master's Degree or higher in Electrical Engineering or ...
Physical Design Engineer (7452)
San Jose, CA · On-site
$155.70K - $160.30K/yr
You will be instrumental in the physical implementation and tapeout of complex test vehicles ... design cycle. Minimum Qualifications * Master's Degree or higher in Electrical Engineering or ...
SoC Physical Design Engineer, STA/Timing
San Jose, CA · On-site
$159.40K - $164.10K/yr
... tapeout) for a highly complex SoC using state of the art process technology. - Work with design ... Good programming skills with Perl and TCL.Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
San Jose, CA · On-site
$159.40K - $164.10K/yr
... tapeout) for a highly complex SoC using state of the art process technology. - Work with design ... Good programming skills with Perl and TCL.Experience with large design STA and Timing Closure.
Principal Engineer - Global Tapeout and Mask Organization
Austin, TX · On-site
$85K - $146K/yr
As a Principal Engineer of Tapeout and Mask Organization , the candidate will work with our global ... This individual will be exposed to complex Electronic Design Automation (EDA) flows, cloud ...
Principal Engineer - Global Tapeout and Mask Organization
Austin, TX · On-site
$85K - $146K/yr
As a Principal Engineer of Tapeout and Mask Organization , the candidate will work with our global ... This individual will be exposed to complex Electronic Design Automation (EDA) flows, cloud ...
SoC Physical Design Engineer, STA/Timing
Austin, TX · On-site
$134.80K - $138.80K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
Austin, TX · On-site
$134.80K - $138.80K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144.40K - $148.60K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144.40K - $148.60K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
$141.50K - $145.70K/yr
... design partition(s) (from netlist to ... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ...
SoC Physical Design Engineer, STA/Timing
$141.50K - $145.70K/yr
... design partition(s) (from netlist to ... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146.70K - $151K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146.70K - $151K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
$134.80K - $138.80K/yr
... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ... Experience with large design STA and/or Timing Closure. Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$134.80K - $138.80K/yr
... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ... Experience with large design STA and/or Timing Closure. Programming skills with Perl and TCL.
HW SOC/ASIC Physical Design Engineer, Senior (US Citizenship Required)
San Diego, CA · On-site
$144.40K - $148.60K/yr
Work closely with backend teams for tapeout preparation and signoff. * Excellent scripting skills ... Engineering, or related field. * 3+ years of experience in physical design, with a focus on clock ...
HW SOC/ASIC Physical Design Engineer, Senior (US Citizenship Required)
San Diego, CA · On-site
$144.40K - $148.60K/yr
Work closely with backend teams for tapeout preparation and signoff. * Excellent scripting skills ... Engineering, or related field. * 3+ years of experience in physical design, with a focus on clock ...
GPU Physical Design Engineer
$134.80K - $138.80K/yr
This role requires a mix of strategic engineering along with hands-on experience in physical design ... design from RTL to tapeout. Description - Work closely with the FE team to understand chip ...
GPU Physical Design Engineer
$134.80K - $138.80K/yr
This role requires a mix of strategic engineering along with hands-on experience in physical design ... design from RTL to tapeout. Description - Work closely with the FE team to understand chip ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144.40K - $148.60K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144.40K - $148.60K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144.40K - $148.60K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144.40K - $148.60K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
... Design Engineers with expertise in top-level signoff for complex SoCs on advanced nodes (7nm/5nm/3nm). Candidates should have multiple full-cycle tapeouts and strong experience in signoff-to-tapeout ...
... Design Engineers with expertise in top-level signoff for complex SoCs on advanced nodes (7nm/5nm/3nm). Candidates should have multiple full-cycle tapeouts and strong experience in signoff-to-tapeout ...
SoC Physical Design Engineer, STA/Timing
Austin, TX · On-site
$134.80K - $138.80K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
Austin, TX · On-site
$134.80K - $138.80K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141.50K - $145.70K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141.50K - $145.70K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
As a Principal Engineer of Tapeout and Mask Organization , the candidate will work with our global ... This individual will be exposed to complex Electronic Design Automation (EDA) flows, cloud ...
As a Principal Engineer of Tapeout and Mask Organization , the candidate will work with our global ... This individual will be exposed to complex Electronic Design Automation (EDA) flows, cloud ...
SoC Physical Design Engineer, STA/Timing
San Jose, CA · On-site
$159.40K - $164.10K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
San Jose, CA · On-site
$159.40K - $164.10K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Programming skills with Perl and TCL. Hands-on experience in STA.Familiar with important aspects of ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141.50K - $145.70K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Minimum BS and 10+ years of relevant industry experienceStrong programming skills with TCL ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141.50K - $145.70K/yr
... tapeout) for a highly complex SOC using state of the art process technology. - Work with design ... Minimum BS and 10+ years of relevant industry experienceStrong programming skills with TCL ...
Tapeout Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do tapeout design engineer jobs pay per year?
As of May 31, 2026, the average yearly pay for tapeout design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Tapeout Design Engineer, and why are they important?
To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.
What are some common challenges Tapeout Design Engineers face during the tapeout process, and how can they be addressed?
Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.
What are Tapeout Design Engineers?
Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.
What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?
| Aspect | Tapeout Design Engineer | ASIC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or related field; knowledge of EDA tools | Bachelor's or Master's in Electrical Engineering or related field; strong digital design skills |
| Work Environment | Semiconductor companies, chip design firms, EDA tool providers | Semiconductor companies, integrated circuit design firms |
| Industry Usage | Focuses on final chip layout and manufacturing readiness | Designs the digital architecture and logic of chips |
While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.
More about Tapeout Design Engineer jobs
What cities are hiring for Tapeout Design Engineer jobs? Cities with the most Tapeout Design Engineer job openings:
What states have the most Tapeout Design Engineer jobs? States with the most job openings for Tapeout Design Engineer jobs include:
What job categories do people searching Tapeout Design Engineer jobs look for? The top searched job categories for Tapeout Design Engineer jobs are:
$141.50K - $145.70K/yr
Full-time
Posted 23 days ago
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product.
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
Description
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
- Work with the Physical Design team, highlighting issues and best practices.
- Help create timing ECO’s for project tapeout.
- Create and maintain scripts and methodologies for analysis and runs.
- Create documentation and help with guidelines/specs.
- Deep analysis of timing paths to identify key issues.
- Implement timing infrastructure.
Preferred Qualifications
Hands-on experience in STA.
Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
Familiar with ECO techniques and implementation.
Good communicator who can accurately describe issues and follow them through to completion.
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience with large design STA and/or Timing Closure.
Programming skills with Perl and TCL.
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
Description
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
- Work with the Physical Design team, highlighting issues and best practices.
- Help create timing ECO’s for project tapeout.
- Create and maintain scripts and methodologies for analysis and runs.
- Create documentation and help with guidelines/specs.
- Deep analysis of timing paths to identify key issues.
- Implement timing infrastructure.
Preferred Qualifications
Hands-on experience in STA.
Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
Familiar with ECO techniques and implementation.
Good communicator who can accurately describe issues and follow them through to completion.
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience with large design STA and/or Timing Closure.
Programming skills with Perl and TCL.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976