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Urgently Hiring Analog Layout Design Engineer Jobs

Analog Layout Design Engineer

Cupertino, CA · On-site

$249K/yr

Analog Layout Design Engineer We are currently looking for an Analog Layout Design Engineer for an onsite position in California with one of our clients. Based on your background, I wanted to reach ...

Analog Layout Design Engineer

Austin, TX · On-site

$200K/yr

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join ... We do not charge any fees during our hiring process. Candidates should never be required to pay ...

Analog Layout Design Engineer

Hillsboro, OR · On-site

$220K/yr

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join ... We do not charge any fees during our hiring process. Candidates should never be required to pay ...

Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 Months, Contract to Hire * Experience with layout of cutting-edge high-performance, high-speed CMOS integrated ...

Analog Layout Engineer

San Jose, CA · On-site

$110K - $300K/yr

This role requires a strong understanding of analog design principles and the ability to work ... To ensure a fair, consistent, and efficient hiring process, all candidates must apply through ...

Analog Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Description We are looking for qualified Analog design engineers who have a good understanding of ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

We are looking forImage Sensor Analog Design Engineer for design and development of next generation ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

We are looking for Image Sensor Analog Design Engineer for design and development of next ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

We are looking for qualified Analog design engineers who have a good understanding of analog ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

We are looking for qualified Analog design engineers who have a good understanding of analog ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

We are looking for qualified Analog circuit design engineers who have a good understanding of ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

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Urgently Hiring Analog Layout Design Engineer information

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How much do urgently hiring analog layout design engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for urgently hiring analog layout design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.
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Infographic showing various Urgently Hiring Analog Layout Design Engineer job openings in the United States as of July 2026, with employment types broken down into 91% Full Time, 5% Part Time, 2% Contract, 1% Nights, and 1% Summer. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.
Analog Layout Design Engineer

Analog Layout Design Engineer

Apton Inc

Cupertino, CA • On-site

$249K/yr

Other

Posted 12 days ago


Job description

Analog Layout Design Engineer

We are currently looking for an Analog Layout Design Engineer for an onsite position in California with one of our clients. Based on your background, I wanted to reach out regarding this opportunity.

Key Requirements:

  • Minimum 6+ years of experience in Analog Layout Design.
  • Experience developing and leading complex IC layouts for high-speed applications in advanced CMOS FinFET technologies (7nm and below) at both block and chip levels.
  • Thorough knowledge of industry-standard EDA tools such as Cadence, Mentor, and Synopsys.
  • Experience with layout of high-performance analog mixed-signal blocks, including Transceivers, CMOS Drivers, High-Speed Data Converters, and PLLs.
  • Expertise in floor planning, block-level routing, and top-level chip assembly.
  • Knowledge of advanced layout techniques, including floor planning, layer generation, thermal-aware layout design, and electro-migration considerations.