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Urgently Hiring Analog Layout Design Engineer Jobs

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Role: Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration ... Experience with FinFET process nodes preferred Experience working with distributed design teams a ...

Trispark Inc

Analog layout Engineer

Manor, TX · On-site

$135K/yr

Analog layout Engineer * Location: Austin, TX * Hybrid * Salary: $135k Note: Please restrict to ... Running complete set of design verification tools available * Great understanding and experience ...

New

Apple

Analog Layout Automation Engineer

San Diego, CA · On-site

$214K/yr

Description As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create ...

Apple

Analog Layout Automation Engineer

San Diego, CA · On-site

$214K/yr

Description As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create ...

United Airlines

Analog Layout Engineer

San Francisco, CA · On-site

$238K/yr

... design and layout organization. In this role, you will contribute to cutting-edge analog and mixed ... hiring and onboarding process. Click the following link for more information on your rights as an ...

Cirrus Logic

Layout Design Engineer

Austin, TX · On-site

The Role In this role, you will work closely with design engineering to complete the layout and ... Design analog & mixed-signal layouts * Understand device matching techniques * Understand signal ...

Apple

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249K/yr

Description As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create ...

United Airlines

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

... design and layout organization. In this role, you will contribute to cutting-edge analog and mixed ... hiring and onboarding process. Click the following link for more information on your rights as an ...

Apple

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249K/yr

Description As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create ...

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Urgently Hiring Analog Layout Design Engineer information

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How much do urgently hiring analog layout design engineer jobs pay per year?

As of Aug 12, 2026, the average yearly pay for urgently hiring analog layout design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.
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Urgently Hiring Analog Layout Design Engineer jobs near you
Infographic showing various Urgently Hiring Analog Layout Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 77% Full Time, 19% Part Time, and 3% Contract. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

Sr. Analog Physical Design Engineer

OmniVision Technologies

Santa Clara, CA • On-site

$156K - $160K/yr

Full-time

Re-posted 19 days ago

Job description

Job Title: Sr. Analog Physical Design Engineer
Job Duties:
  • Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC's performance with minimum silicon area.
  • Conduct cross products column ADC layout comparison and IP layout development and maintenance.
  • Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality.
  • Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
  • Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed.
  • Apply SKILL script to improve productivity and design robustness.
  • Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre.
  • Execute top-level layout and coordinate layout resources and schedules for all modules.
  • Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy.
  • Lead top-level implementation from floorplan through GDS tape-out.
  • Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices.
Requirements:
Require Master's degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
Require 2 years of experience in CMOS image sensor IC layout design.
Require the following experience or skills:
  • Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges.
  • Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications.
  • Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P.
  • Front-end and back-end ASIC design flows.
  • Experience in stacked chip process flow and related design considerations.
  • Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files.
  • Advanced layout skills such ascommon-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc.
  • Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop.
  • Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl.
  • Expertise in low-power, high-precision, high speed analog layout design techniques.
  • Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

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