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Serdes Design Jobs (NOW HIRING)

Apple

SerDes Design and Validation Engineer

San Diego, CA · On-site

$214K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

Apple

SerDes Design and Validation Engineer

Austin, TX · On-site

$200K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

Apple

SerDes Design and Validation Engineer

Austin, TX

$122K - $214K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

Apple

SerDes Design and Validation Engineer

Austin, TX

$129K - $225K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

Apple

SerDes Design and Validation Engineer

Austin, TX

$175K - $308K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

Apple

SerDes Design and Validation Engineer

Austin, TX

$175K - $308K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

Apple

SerDes Design and Validation Engineer

Austin, TX · On-site

$200K/yr

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes IP. In this highly visible role, you will contribute to the design, integration and ...

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Serdes Design information

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$14

$27

$44

How much do serdes design jobs pay per hour?

As of Aug 5, 2026, the average hourly pay for serdes design in the United States is $27.99, according to ZipRecruiter salary data. Most workers in this role earn between $21.88 and $31.73 per hour, depending on experience, location, and employer.

What are some common challenges faced by SerDes design engineers, and how can they be addressed?

Serdes Design engineers often encounter challenges related to high-speed signal integrity, power consumption, and meeting stringent timing requirements. Debugging issues such as jitter, crosstalk, and electromagnetic interference requires a strong understanding of both analog and digital domains, as well as proficiency in simulation tools. Collaboration with verification, layout, and system teams is essential to ensure the design meets performance and compliance standards. Staying updated on the latest process technologies and industry standards can help address these challenges effectively.

What is the difference between Serdes Design vs FPGA Design Engineer?

AspectSerdes DesignFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in high-speed signalingBachelor's or Master's in Electrical or Computer Engineering, with FPGA focus
Work EnvironmentSemiconductor companies, high-speed circuit labsElectronics companies, FPGA development teams
Industry UsageHigh-speed data communication, networking hardwareDigital system development, embedded systems
Common Search/ComparisonYesYes

Serdes Design focuses on developing high-speed serial transceivers for data communication, requiring expertise in analog and high-speed digital circuits. FPGA Design Engineers develop digital logic on FPGA platforms, often integrating Serdes modules but with broader responsibilities in digital system design. While both roles overlap in digital electronics and high-speed signaling, Serdes Design is specialized in transceiver architecture, whereas FPGA Design Engineers work on implementing entire digital systems on FPGA chips.

What is SerDes design?

SerDes design refers to the creation and optimization of Serializer/Deserializer circuits, which are used to convert data between serial and parallel formats. These circuits are essential in high-speed data communication systems, enabling efficient transmission of data over limited pin counts or long distances. SerDes designers work on ensuring signal integrity, minimizing power consumption, and meeting specific data rate requirements for applications such as networking, telecommunications, and computer hardware.

What are the key skills and qualifications needed to thrive as a SerDes design engineer?

To thrive as a SerDes Design Engineer, you need a solid background in electrical engineering, high-speed circuit design, and signal integrity, typically demonstrated by a relevant degree. Familiarity with EDA tools such as Cadence or Synopsys, experience with simulation software, and sometimes knowledge of industry standards like PCIe or USB are essential. Strong analytical thinking, attention to detail, and effective communication skills help in solving complex design issues and collaborating with cross-functional teams. These competencies are crucial for developing reliable, high-performance serial interfaces that meet stringent industry requirements.
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Serdes Design jobs near you
Infographic showing various Serdes Design job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $58,220 per year, or $28 per hour.

Senior/Principal SerDes Design Engineer

Celero Communications, Inc.

Irvine, CA • On-site

$150K - $250K/yr

Full-time

Posted 4 days ago

Job description

Senior to Principal SerDes Design Engineer roles
Locations: Irvine, CA or San Jose, CA
About the job
We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.
What You Will Do
• Define architecture, specifications, and circuit topologies for next-generation SerDes  
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting 
• Design high-performance analog/mixed-signal circuits in advanced node technologies  
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs 
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area 
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts 
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets  
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab 
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
What You Will Bring
• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design 
• Proven record of taking high-speed SerDes design to tape-out and volume production 
• Experience in lab bring-up, characterization, and debugging designs that reach out production  
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)  
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs 
• Strong communication and documentation skills 
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)