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Serdes Design Jobs (NOW HIRING)

SerDes Circuit Design Engineer

Waltham, MA · On-site

$217K/yr

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

SerDes Circuit Design Engineer

San Francisco, CA · On-site

$238K/yr

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

SerDes Circuit Design Engineer

Melbourne, FL · On-site

$187K/yr

SerDes Circuit Design Engineer We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline ...

SerDes Circuit Design Engineer

Melbourne, FL · On-site

$187K/yr

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

SerDes Circuit Design Engineer

San Francisco, CA · On-site

$238K/yr

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

SerDes Circuit Design Engineer

Austin, TX · On-site

$200K/yr

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

SerDes Circuit Design Engineer

Austin, TX · On-site

$200K/yr

SerDes Circuit Design Engineer We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline ...

SerDes Circuit Design Engineer

Waltham, MA · On-site

$217K/yr

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team ... In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ...

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Serdes Design information

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$14

$27

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How much do serdes design jobs pay per hour?

As of Jun 5, 2026, the average hourly pay for serdes design in the United States is $27.99, according to ZipRecruiter salary data. Most workers in this role earn between $21.88 and $31.73 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a SerDes Design Engineer, and why are they important?

To thrive as a SerDes Design Engineer, you need a solid background in electrical engineering, high-speed circuit design, and signal integrity, typically demonstrated by a relevant degree. Familiarity with EDA tools such as Cadence or Synopsys, experience with simulation software, and sometimes knowledge of industry standards like PCIe or USB are essential. Strong analytical thinking, attention to detail, and effective communication skills help in solving complex design issues and collaborating with cross-functional teams. These competencies are crucial for developing reliable, high-performance serial interfaces that meet stringent industry requirements.

What are some common challenges faced by Serdes Design engineers, and how can they be addressed?

Serdes Design engineers often encounter challenges related to high-speed signal integrity, power consumption, and meeting stringent timing requirements. Debugging issues such as jitter, crosstalk, and electromagnetic interference requires a strong understanding of both analog and digital domains, as well as proficiency in simulation tools. Collaboration with verification, layout, and system teams is essential to ensure the design meets performance and compliance standards. Staying updated on the latest process technologies and industry standards can help address these challenges effectively.

What is SerDes design?

SerDes design refers to the creation and optimization of Serializer/Deserializer circuits, which are used to convert data between serial and parallel formats. These circuits are essential in high-speed data communication systems, enabling efficient transmission of data over limited pin counts or long distances. SerDes designers work on ensuring signal integrity, minimizing power consumption, and meeting specific data rate requirements for applications such as networking, telecommunications, and computer hardware.

Are design engineers well paid?

Design engineers, including those working in Serdes (Serializer/Deserializer) circuit design, typically earn competitive salaries that vary based on experience, location, and industry. In technology sectors, salaries often range from mid to high six figures for experienced professionals with specialized skills in high-speed digital design and FPGA or ASIC development. Certifications and proficiency with industry tools can also influence compensation levels.

What is the difference between Serdes Design vs FPGA Design Engineer?

AspectSerdes DesignFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in high-speed signalingBachelor's or Master's in Electrical or Computer Engineering, with FPGA focus
Work EnvironmentSemiconductor companies, high-speed circuit labsElectronics companies, FPGA development teams
Industry UsageHigh-speed data communication, networking hardwareDigital system development, embedded systems
Common Search/ComparisonYesYes

Serdes Design focuses on developing high-speed serial transceivers for data communication, requiring expertise in analog and high-speed digital circuits. FPGA Design Engineers develop digital logic on FPGA platforms, often integrating Serdes modules but with broader responsibilities in digital system design. While both roles overlap in digital electronics and high-speed signaling, Serdes Design is specialized in transceiver architecture, whereas FPGA Design Engineers work on implementing entire digital systems on FPGA chips.

More about Serdes Design jobs
What states have the most Serdes Design jobs? States with the most job openings for Serdes Design jobs include:
Infographic showing various Serdes Design job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 87% Physical, 8% Hybrid, and 5% Remote job distribution, with an average salary of $58,220 per year, or $28 per hour.
Lead SERDES RTL Design Engineer

Lead SERDES RTL Design Engineer

Advanced Micro Devices, Inc

San Jose, CA • Hybrid

$117K - $160K/yr

Full-time

Posted 20 days ago


Advanced Micro Devices rating

8.4

Company rating: 8.4 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

25th of 139 rated electronics manufacturers


Job description


WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  



THE ROLE:

SerDes Technology group is seeking a talented, motivated and self-driven SerDes Micro Architect with expertise in high-speed SerDes RTL design. You have had significant success driving architecture and product requirements, integrating complex IPs into SOC. You have deep knowledge of digital design methodology and are meticulous about Power, Performance and Area. In this role, you will work with a world-class team to drive the definition of next generation high-speed SerDes IPs.
THE PERSON:

If you have a keen interest in high-speed SerDes and digital RTL design, excel in teamwork and possess strong communication skills, your profile aligns well with our requirements. We are seeking someone who is innovative, detail-oriented and possesses excellent problem-solving skills to join our design team. 

KEY RESPONSIBILITIES:

  • Define micro-architecture requirements for SerDes IPs, drive technical specifications to meet those requirements, and provide technical direction to execution teams
  • Design and development of digital logic blocks in leading edge technology nodes
  • Work with cross-functional teams to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
  • Work closely with design teams for area and floorplan refinement, verification test plan reviews, timing targets, emulation plans, pre-Si bug resolution and performance/power verification sign offs
  • Support post-Si teams for product performance, power and functional issues debug/resolution

 PREFERRED EXPERIENCE:

  • Excellent communication, management, and presentation skills
  • Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
  • Experience in driving the definition of high-speed SerDes IPs, with strong knowledge on the application in PCIe and Ethernet
  • Experience in system architecture, CPU & IP Integration, power and clock management design
  • Experience in RTL design, verification, synthesis and STA in high performance design
  • Good understanding of adaptation and calibration algorithms
  • Good understanding of link equalization, clock and data recovery
  • Good understanding of digital signal processing
  • Good knowledge of SystemVerilog and UVM

 ACADEMIC CREDENTIALS:

  • Bachelor’s or Master’s degree in related discipline

LOCATION: San Jose, CA

#LI-MO2

#LI-HYBRID



Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Qualifications:

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Education:UNAVAILABLEEmployment Type: FULL_TIME