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Tapeout Design Engineer Jobs (NOW HIRING)

OmniVision Technologies

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

onsemi

Design Engineer

Scottsdale, AZ · On-site

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.

onsemi

Design Engineer

Scottsdale, AZ · On-site

As a Principal Design Engineer located in Scottsdale, Arizona, you will have the opportunity to ... Highly skilled in Cadence design tools for schematic capture, simulations, DRC, LVS for tapeout.

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Will work of full project lifecycle from inception to tapeout. Qualifications: * BSEE with 5+ years ...

Tenstorrent

Physical Design Engineer, PnR

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions ... You'll own the complete implementation flow from synthesis to tapeout, working alongside world ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Will work of full project lifecycle from inception to tapeout. Qualifications: * BSEE with 5+ years ...

Astera Labs

Principal Digital Design Engineer

San Jose, CA · On-site

$159K/yr

... to tapeout. * Have experience with timing fixes, area and power optimizations, and resolving ... Serve as the responsible engineer for at least one critical design block, including architecture ...

Lumilens

Sr. Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard ... Engineering, or a related field. * Experience: 8+ years of hands-on physical design experience ...

New

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

Tapeout + productization experience STA Engineer * SoC-level timing analysis & closure * PrimeTime, Tempus, or similar Physical Design Engineer * Floorplanning, CTS, routing, signoff * Timing ...

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All JobsTapeout Design Engineer Jobs

Tapeout Design Engineer information

See salary details

$40.5K

$88.2K

$158.5K

How much do tapeout design engineer jobs pay per year?

As of Jul 12, 2026, the average yearly pay for tapeout design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Tapeout Design Engineer, and why are they important?

To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.

What are Tapeout Design Engineers?

Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.

What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?

AspectTapeout Design EngineerASIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering or related field; strong digital design skills
Work EnvironmentSemiconductor companies, chip design firms, EDA tool providersSemiconductor companies, integrated circuit design firms
Industry UsageFocuses on final chip layout and manufacturing readinessDesigns the digital architecture and logic of chips

While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.

What are some common challenges Tapeout Design Engineers face during the tapeout process, and how can they be addressed?

Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.
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Tapeout Design Engineer jobs near you
SoC Design Engineer

SoC Design Engineer

OmniVision Technologies

Santa Clara, CA • On-site

$156K - $160K/yr

Other

Re-posted 4 days ago

Job description

Job Title: SoC Design Engineer
Job Duties:
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP design, analysis, integration, and validation. Collaborate with physical design teams on floor-planning, timing closure, and DFT implementation. Conduct timing control logic design and static timing analysis (STA) for sensor interfaces and mixed-signal integration. Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline according to PRD/design specification and system architecture of SoC products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc. Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital and analog engineers for system design, integration and validation. Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation. Work with algorithm and application engineers for project-based microarchitecture improvements. Conduct silicon validation, debugging and tuning.
Requirements:
Master's degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field.
Required skills and/or academic training in the following:
  • Arithmetic circuit design related to general datapath circuits, ML and AI circuits.
  • Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and debug.
  • Design and design debug with System Verilog; Logic design and analysis.
  • Processing Subsystem, including superscalar out-of-order cores, multicore and heterogeneous processors, and purpose-specific accelerators.
  • Design tools, such as microarchitecture simulators, RTL synthesis tools, and modeling for area, power, and thermal.
  • FPGA platforms to compute acceleration.
  • FPGAs technology, architecture and applications.
  • Register-Transfer Level (RTL) hardware design.
  • Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks.
  • Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal chip design.
  • Full-chip integration and verification for tapeout.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

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