ZipRecruiter

Log In

1

Tapeout Design Engineer Jobs (NOW HIRING)

OMNIVISION

Analog Design Engineer

Santa Clara, CA

Participate in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization. Requirements: Master's degree in Electrical Engineering ...

Tektronix

ASIC Physical Design Engineer

Boulder, CO · On-site

$143K - $147K/yr

Our inclusive engineering culture is hardworking, inquisitive, and always eager to learn and grow ... timing-closed, manufacturable, tapeout-ready design.Develop and maintain scripts, flows ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

... in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization. Requirements: Master's degree in Electrical Engineering, Computer ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA

$156K - $160K/yr

... in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization. Requirements: Master's degree in Electrical Engineering, Computer ...

SambaNova

Senior Hardware Design Engineer

Austin, TX · On-site

A block stays with the engineer who wrote it through PPA closure, tapeout, and bring-up, so you debug your own design in silicon. About the role SambaNova Senior Hardware Design Engineers design ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

OmniVision Technologies

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

previous pagenext page

Showing results 21-40

All JobsTapeout Design Engineer Jobs

Tapeout Design Engineer information

See salary details

$40.5K

$88.2K

$158.5K

How much do tapeout design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for tapeout design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is a tapeout design engineer?

Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.

What are the key skills and qualifications needed to thrive as a tapeout design engineer?

To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.

What are some common challenges tapeout design engineers face during the tapeout process, and how can they be addressed?

Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.

What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?

AspectTapeout Design EngineerASIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering or related field; strong digital design skills
Work EnvironmentSemiconductor companies, chip design firms, EDA tool providersSemiconductor companies, integrated circuit design firms
Industry UsageFocuses on final chip layout and manufacturing readinessDesigns the digital architecture and logic of chips

While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.

More about Tapeout Design Engineer jobs

What cities are hiring for Tapeout Design Engineer jobs?

Cities with the most Tapeout Design Engineer job openings:

What states have the most Tapeout Design Engineer jobs?

States with the most job openings for Tapeout Design Engineer jobs include:

What are popular job titles related to Tapeout Design Engineer jobs?

For Tapeout Design Engineer jobs, the most frequently searched job titles are:

Tapeout Design Engineer jobs near you
Infographic showing various Tapeout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Analog Design Engineer

Santa Clara, CA

OMNIVISION
Software Development • 1 - 5K employees
Learn more about OMNIVISIONexternal

Full-time

Re-posted 20 days ago

Key responsibilities

  • Design and develop analog circuits for CMOS Image Sensors, including schematic design, simulation, and verification.

  • Collaborate with layout engineers to optimize device matching, symmetry, shielding, and routing for noise performance and area efficiency.

  • Perform system-level analog simulation, post-layout verification, and process, voltage, and temperature (PVT) analysis to ensure performance and robustness.

Job description

•    Conduct end-to-end design and development of advanced CMOS Image Sensor (CIS) technologies with a focus on transistor-level design, simulation, and verification of analog circuits using Cadence Virtuoso. 
•    Design analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p. 
•    Perform complete schematic design flow, closely collaborate with layout engineers on device matching, symmetry, shielding, and routing for optimal noise performance and area efficiency. 
•    Carry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC), Layout vs. Schematic (LVS), and Physical Electrical Rule Check (PERC) using Calibre.
•    Conduct system-level analog simulation and CIS signal chain verification to ensure correct signal propagation from pixel through the entire analog front-end to digital input interface.
•    Execute extensive process, voltage and temperature (PVT) and Monte Carlo simulations to evaluate functional robustness, and performance margins. 
•    Perform IR drop analysis and power integrity verification to ensure reliable power delivery and layout feasibility.
•    Utilize Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice for block-level and full-chain validation under realistic operating scenarios.
•    Develop and maintain automation scripts in Python and Perl to streamline simulation flow, including netlist generation, corner sweeping, batch result parsing, and yield analysis. Build scalable toolchains to support multi-corner, multi-mode simulations and regression testing, enhancing design turnaround and validation coverage.
•    Collaborate with cross-functional teams with digital design, verification, process, and test to define analog-digital interface specifications, establish timing constraints, support readout calibration algorithms, and debug post-silicon performance issues. 
•    Participate in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization.
Requirements:
Master’s degree in Electrical Engineering, Computer Engineering, or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems Design, VLSI system design, and VLSI Signal Processing.
Must possess the following skills:
•    Analog circuits using MOS models,
•    Operational amplifier and current mirror design,
•    Noise analysis and feedback system,
•    Evaluation of offset distortion and nonlinearity,
•    Functional verification using ModelSim,
•    Static timing analysis, power and area estimation,
•    Standard-cell based logic and physical synthesis,
•    Hardware scheduling and retiming,
•    Number representation and digital arithmetic,
•    Full analog IC design flow,
•    Post-tapeout chip testing and validation,
•    VLSI circuit and system design using Verilog,
•    Architecture design space exploration,
•    Spectrum Analyzer.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.