We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our ...
OR · On-site
Track advances in AI, EDA, and hardware design research, evaluating their applicability and guiding ... High-level programming skills including experience with Python, PERL, Make, and shell scripting.
OR · Hybrid
In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip ... Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
OR · On-site
$190K - $280K/yr
The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing ...
As a member of our verification team, you'll understand the design & implementation with focus on ... Engineering or equivalent experience * Exposure to Computer Architecture, ASIC design and ...
As a member of our verification team, you'll understand the design & implementation with focus on ... Engineering or equivalent experience * Exposure to Computer Architecture, ASIC design and ...
SENIOR DESIGN ENGINEER
Harrisburg, OR · On-site
Senior Design Engineers report to the Vice President of Engineering and serve as senior technical resources for KRPI's precast and prestressed concrete design work. Unlike Design Engineers focused ...
SENIOR DESIGN ENGINEER
Harrisburg, OR · On-site
Senior Design Engineers report to the Vice President of Engineering and serve as senior technical resources for KRPI's precast and prestressed concrete design work. Unlike Design Engineers focused ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $200K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $200K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Senior Asic Design Engineer information
See Oregon salary details
$148K - $155.7K
4% of jobs
$155.7K - $163.3K
12% of jobs
$167.8K is the 25th percentile. Wages below this are outliers.
$163.3K - $170.9K
16% of jobs
$170.9K - $178.6K
16% of jobs
The median wage is $180.2K / yr.
$178.6K - $186.2K
13% of jobs
$186.2K - $193.9K
8% of jobs
$200.7K is the 75th percentile. Wages above this are outliers.
$193.9K - $201.5K
7% of jobs
$201.5K - $209.2K
6% of jobs
$209.2K - $216.8K
7% of jobs
$216.8K - $224.4K
5% of jobs
$224.4K - $232.1K
5% of jobs
$148K
$187.8K
$232.1K
How much do senior asic design engineer jobs pay per year?
As of Aug 10, 2026, the average yearly pay for senior asic design engineer in Oregon is $187,830.00, according to ZipRecruiter salary data. Most workers in this role earn between $168,100.00 and $206,200.00 per year, depending on experience, location, and employer.
What does a senior ASIC design engineer do?
A Senior ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in a wide range of electronic devices. They lead the architecture, implementation, and verification of complex digital or mixed-signal circuits, often collaborating with cross-functional teams. This senior role involves optimizing designs for performance, power, and area while ensuring that the final product meets stringent technical and quality requirements. Additionally, they may mentor junior engineers and contribute to design methodologies and best practices within the organization.
What are the key skills and qualifications needed to thrive as a senior ASIC design engineer?
To thrive as a Senior ASIC Design Engineer, you need deep expertise in digital and/or analog circuit design, strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and a relevant engineering degree. Familiarity with EDA tools such as Synopsys, Cadence, and Mentor Graphics, as well as experience with simulation, synthesis, and verification methodologies, is typically required. Outstanding problem-solving, collaboration, and communication skills set top performers apart in this role. These competencies ensure efficient design cycles, robust chip functionality, and successful delivery of complex semiconductor projects.
What is the difference between Senior Asic Design Engineer vs Digital IC Design Engineer?
| Aspect | Senior Asic Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering, VLSI, or related fields; experience in ASIC design | Bachelor's/Master's in Electrical Engineering, VLSI, or related fields; focus on digital circuit design |
| Work Environment | Design teams in semiconductor or tech companies, hardware development labs | Integrated circuit design teams, research labs, semiconductor companies |
| Employer & Industry Usage | Used in ASIC development, FPGA design, hardware acceleration | Used in digital chip design, FPGA development, digital system integration |
The main difference is that a Senior Asic Design Engineer specializes in designing application-specific integrated circuits, often leading complex projects, while a Digital IC Design Engineer focuses on digital circuit design within integrated circuits. Both roles require similar educational backgrounds and work environments but differ in project scope and specialization.
What are some common challenges senior ASIC design engineers face when collaborating with cross-functional teams?
Senior ASIC Design Engineers often work closely with verification, software, and systems teams throughout the development cycle. One common challenge is ensuring clear communication of design specifications and changes, as misunderstandings can lead to integration issues or delays. Balancing multiple project timelines and adapting to evolving requirements from other departments can also be demanding. Building strong, collaborative relationships and using robust documentation and project management tools are key to overcoming these challenges.
What are the most commonly searched types of Asic Design Engineer jobs in Oregon? The most popular types of Asic Design Engineer jobs in Oregon are:
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Full-time
Re-posted 7 days ago
Nvidia rating
9.6
Based on 17 frontline employees who took The Breakroom Quiz
8th of 242 rated software companies
Job description
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team! For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research.
Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life. As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/
What you'll be doing:
In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.
You will be responsible for micro-architecture using sophisticated verification methodologies.
As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.
What we need to see:
Bachelors or Master's Degree (or equivalent experience)
3+ years of relevant verification experience.
Experience in architecting test bench environments for unit level verification.
Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
Prior Design or Verification experience of Coherent high-speed interconnects.
Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful.
Strong background developing TB's from scratch using SV and UVM methodology is desired.
C++ programming language experience, scripting ability and an expertise in System Verilog.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Strong debugging and analytical skills.
Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.
NVIDIA is widely considered to be one of the technology world's most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993