Rtl Design Jobs in Oregon (NOW HIRING)

Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!
Description
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use for modifying, analyzing, and verifying RTL.
In this role, you will support RTL gatekeeping infrastructure of design and verification collateral as well as soft IP development and release methodologies. Additionally, you will contribute to Perforce administration, ensuring the integrity and performance of our version control ecosystem. You will have the opportunity to maintaining a centralized configuration management system that enables different design views to be loaded into any Front-End flow.
An important key aspect of this position is driving innovation through building generative AI solutions across all of these systems and identifying opportunities where AI can accelerate engineering productivity and improve infrastructure reliability. Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at Apple.
The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable infrastructure solutions across RTL Design and DV teams within Apple’s HWTech organization.
In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the different design groups:
To create, monitor, and maintain high quality infrastructure and flows that enable Apple Silicon to produce chips that enable Apple's best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apple’s chip design efforts.
Preferred Qualifications
Experience with Front-End EDA tools such as Clock Domain Crossing, Reset Domain Crossing or Lint
Understanding of Front-End RTL Build or Construction flows
Excellent communication, debug and root causing skills
Customer-oriented mindset and support experience
Experience in contributing to large-scale software system development from specification to deployment
•MSEE/CE/CS preferred
Minimum Qualifications
Minimum of BS degree
Expertise in programming in Python or Perl
Knowledge in Verilog and SystemVerilog
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.