DFT Architect
San Jose, CA · On-site
$203K/yr
Manage DFT activities across architecture, design implementation, verification, and test implementation for new products. * The role is in AMD global quality and operation organization driving best ...
DFT Architect
San Jose, CA · On-site
$203K/yr
Manage DFT activities across architecture, design implementation, verification, and test implementation for new products. * The role is in AMD global quality and operation organization driving best ...
DFT Engineer
San Jose, CA · On-site
$101K - $162K/yr
The successful candidate will be working on DFT programs all the way from chip level DFT ... Project management capabilities to track and prioritize competing deliverables across cross ...
DFT Engineer
San Jose, CA · On-site
$101K - $162K/yr
The successful candidate will be working on DFT programs all the way from chip level DFT ... Project management capabilities to track and prioritize competing deliverables across cross ...
Manage DFT activities across architecture, design implementation, verification, and test implementation for new products. * The role is in AMD global quality and operation organization driving best ...
Manage DFT activities across architecture, design implementation, verification, and test implementation for new products. * The role is in AMD global quality and operation organization driving best ...
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
DFT Engineer
San Jose, CA · On-site
$101K - $162K/yr
The successful candidate will be working on DFT programs all the way from chip level DFT ... Project management capabilities to track and prioritize competing deliverables across cross ...
DFT Engineer
San Jose, CA · On-site
$101K - $162K/yr
The successful candidate will be working on DFT programs all the way from chip level DFT ... Project management capabilities to track and prioritize competing deliverables across cross ...
We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Need knowledge of design for test (DFT) structures such as scan chains ...
We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Need knowledge of design for test (DFT) structures such as scan chains ...
ASIC DFT Engineer
San Jose, CA · On-site
$121K - $195K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$121K - $195K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
$121K - $195K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
$121K - $195K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
Rockford, IL · On-site
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 ... Regards Nirdosh Singh Sr. Account Manager | Tanisha Systems Inc. Phone: 732-377-3299 x 599 Email ...
ASIC DFT Engineer
Rockford, IL · On-site
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 ... Regards Nirdosh Singh Sr. Account Manager | Tanisha Systems Inc. Phone: 732-377-3299 x 599 Email ...
DFT Engineer
Richardson, TX · On-site
$106K - $184K/yr
Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features under manager guidance. * Execute test pattern generation and optimization to minimize test time ...
DFT Engineer
Richardson, TX · On-site
$106K - $184K/yr
Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features under manager guidance. * Execute test pattern generation and optimization to minimize test time ...
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
DFT Engineer
Austin, TX · On-site
$106K - $184K/yr
Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features under manager guidance. * Execute test pattern generation and optimization to minimize test time ...
DFT Engineer
Austin, TX · On-site
$106K - $184K/yr
Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features under manager guidance. * Execute test pattern generation and optimization to minimize test time ...
DFT Application Engineer
Phoenix, AZ · On-site
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
DFT Application Engineer
Phoenix, AZ · On-site
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Project management capabilities to track and prioritize competing deliverables across cross ...
ASIC DFT Engineer
San Jose, CA · On-site
$141K - $226K/yr
Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose ... Project management capabilities to track and prioritize competing deliverables across cross ...
Principal DFT Engineer
OR · Remote
$180K - $220K/yr
Experience managing DFT in multi-voltage/power-gated designs-crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be ...
Principal DFT Engineer
OR · Remote
$180K - $220K/yr
Experience managing DFT in multi-voltage/power-gated designs-crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be ...
Principal DFT Engineer
$180K - $220K/yr
Experience managing DFT in multi-voltage/power-gated designs-crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be ...
Principal DFT Engineer
$180K - $220K/yr
Experience managing DFT in multi-voltage/power-gated designs-crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be ...
Dft Manager information
See salary details
$28.5K - $36.2K
9% of jobs
$36.2K - $44K
15% of jobs
$44.3K is the 25th percentile. Wages below this are outliers.
$44K - $51.7K
16% of jobs
The median wage is $57.3K / yr.
$51.7K - $59.4K
14% of jobs
$66.5K is the 75th percentile. Wages above this are outliers.
$59.4K - $67.1K
23% of jobs
$67.1K - $74.9K
8% of jobs
$74.9K - $82.6K
3% of jobs
$82.6K - $90.3K
3% of jobs
$90.3K - $98K
4% of jobs
$98K - $105.8K
2% of jobs
$105.8K - $113.5K
2% of jobs
$28.5K
$62.7K
$113.5K
How much do dft manager jobs pay per year?
As of Jun 27, 2026, the average yearly pay for dft manager in the United States is $62,661.00, according to ZipRecruiter salary data. Most workers in this role earn between $45,000.00 and $69,000.00 per year, depending on experience, location, and employer.
What are DFT Managers?
DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.
What is the difference between Dft Manager vs Dft Engineer?
| Aspect | Dft Manager | Dft Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniques | Bachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools |
| Work Environment | Oversees DFT teams, manages testing strategies, collaborates with design and manufacturing | Performs DFT design, implements test structures, analyzes test data |
| Industry Usage | Used in semiconductor and integrated circuit industries for testability management | Used in semiconductor design for implementing testability features |
The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.
What are some common challenges a DFT Manager faces when coordinating between design and test teams?
A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.
What are the key skills and qualifications needed to thrive as a DFT (Design for Test) Manager, and why are they important?
To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.
More about Dft Manager jobs
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What states have the most Dft Manager jobs? States with the most job openings for Dft Manager jobs include:
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Advanced Micro Devices rating
8.4
Based on 7 frontline employees who took The Breakroom Quiz
22nd of 139 rated electronics manufacturers
Job description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves working with design architecture, design DFT/DFX, design block owners and physical design teams with ATE manufacturing environment, silicon debug, product quality and test cost perspectives. The DFT architect is expected to apply past technical knowledge, learn new cutting-edge technologies and collaborate with teams to arrive at best manufacturable solution. The DFT architect will ensure that DFT implementation is completed by architecture design specifications. This is the role of overseeing early architecture design definition to successful silicon high-volume production.
THE PERSON:
We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
LOCATION:
San Jose, California, United States
This role is not eligible for visa sponsorship.
#LI-AJ1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves working with design architecture, design DFT/DFX, design block owners and physical design teams with ATE manufacturing environment, silicon debug, product quality and test cost perspectives. The DFT architect is expected to apply past technical knowledge, learn new cutting-edge technologies and collaborate with teams to arrive at best manufacturable solution. The DFT architect will ensure that DFT implementation is completed by architecture design specifications. This is the role of overseeing early architecture design definition to successful silicon high-volume production.
THE PERSON:
We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization.
KEY RESPONSIBILITIES:
- Promote ATE & production test environment, test cost and test quality enhancements in future AMD products through DFT architecture definitions and specifications
- Manage DFT activities across architecture, design implementation, verification, and test implementation for new products.
- The role is in AMD global quality and operation organization driving best manufacturing test solution through early product definition and pre & post silicon activities
- Work closely with design teams and make sure DFT structures are correctly implemented.
- Drive internal DFT teams to correctly implement and create test solutions
- Drive firmware driven test solutions
- Plan for diagnosability and yield improvement
PREFERRED EXPERIENCE:
- Significant DFT engineering experience through DFT pre and post silicon cycles
- Experience in creating and implementing complex chip-level DFT architecture
- Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
- Strong MBIST knowledge
- Experience in PHY, high-speed IO, digital communication and functional test development
- Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
- Good understanding of Verilog, synthesis, physical implementation and STA
- Good understanding of verification methodology
- Knowledge of FPGA logic, synthesis and design flow is a plus
- Knowledge of embedded design and firmware methodology is a plus
- Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
- Good communication skills and works well in a group environment that spans across continents
ACADEMIC CREDENTIALS:
- MS or Ph.D. in Electrical/Electronic/Computer Engineering
LOCATION:
San Jose, California, United States
This role is not eligible for visa sponsorship.
#LI-AJ1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US